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automotive power data sheet rev. 1.1, 2012-03-08 TLE9833QX microcontroller with lin and power s witches for automotive applications
edition 2012-03-08 published by infineon technologies ag 81726 munich, germany ? 2012 infineon technologies ag all rights reserved. legal disclaimer the information given in this docu ment shall in no event be regarded as a guarantee of conditions or characteristics. with respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, infine on technologies hereby disclaims any and all warranties and liabilities of any kind, including witho ut limitation, warranties of non-infrin gement of intellectua l property rights of any third party. information for further information on technology, delivery terms and conditions and prices, please contact the nearest infineon technologies office ( www.infineon.com ). warnings due to technical requirements, components may contain dangerous substances. for information on the types in question, please contact the nearest infineon technologies office. infineon technologies compon ents may be used in life-su pport devices or systems only with the express written approval of infineon technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system or to affect the safe ty or effectiveness of that de vice or system. life support devices or systems are intended to be implanted in the hu man body or to support an d/or maintain and sustain and/or protect human life. if they fail, it is reasonable to assume that the health of the user or other persons may be endangered.
TLE9833QX table of contents data sheet 3 rev. 1.1, 2012-03-08 table of contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1 summary of features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.1 device types / ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.2 abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2 general device information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.1 pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.2 pin definitions and functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.1 power management unit (pmu) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.1.1 voltage regulator 5.0v (vddp) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.1.2 voltage regulator 1.5v (vddc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.1.3 external voltage regulator 5.0v (vddext) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.2 system control unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.2.1 system control unit - power modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.2.2 system control unit - digital part . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.3 xc800 core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.4 memory architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 3.5 flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 3.6 watchdog timer 1 (wdt1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 3.7 watchdog timer (wdt) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 3.8 interrupt system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 3.9 multiplication/division unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 3.10 parallel ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 3.11 timer 0 and timer 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 3.12 timer 2 and timer 21 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 3.13 timer 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 3.14 capture/compare unit 6 (ccu6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 3.15 uart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 3.16 lin transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 3.17 high-speed synchronous serial interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 3.18 measurement unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 3.19 measurement core module (incl. adc2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 3.20 analog digital converter (adc1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 3.21 high voltage monitor input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 3.22 high side switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 3.23 low side switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 3.24 pwm generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 3.25 debug system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 4 application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 4.1 electric drive application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 4.2 connection of n.c. pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 4.3 connection of adcgnd pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 4.4 connection of exposed pad . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 4.5 voltage regulators-blocking capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 4.6 additional external components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 4.7 esd tests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 5 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 table of contents
TLE9833QX table of contents data sheet 4 rev. 1.1, 2012-03-08 5.1 general characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 5.1.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 5.1.2 functional range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 5.1.3 current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 5.1.4 thermal resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 5.1.5 timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 5.2 power management unit (pmu) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 5.2.1 pmu i/o supply parameters vddp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 5.2.2 pmu core supply parameters vddc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 5.2.3 vddext voltage regulator 5.0v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 5.3 system clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 5.3.1 oscillators and pll . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 5.3.2 external clock parameters xtal1, xtal2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 5.4 flash parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 5.5 parallel ports (gpio) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 5.5.1 functional range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 5.5.2 dc parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 5.6 lin transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 5.6.1 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 5.7 high-speed synchronous serial interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 5.8 measurement unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 5.8.1 analog digital converter 8-bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 5.8.2 measurement unit (vbat_sense - suppl y voltage attenuator) . . . . . . . . . . . . . . . . . . . . . . . . . . 79 5.8.3 measurement functions monitoring inpu t voltage attenuator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 5.8.4 temperature sensor module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 5.9 adc - 10-bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 5.9.1 varef . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 5.9.1.1 functional range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 5.9.1.2 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 5.9.2 analog/digital converter parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 5.10 high-voltage monitor input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 5.11 high side switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 5.11.1 functional range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 5.11.2 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 5.12 low side switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 5.12.1 functional range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 5.12.2 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 6 package outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 7 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
TLE9833QX summary of features data sheet 5 rev. 1.1, 2012-03-08 1 summary of features ? high performance xc800 core ? compatible to standard 8051 core ? up to 40 mhz clock frequency ? two clocks per machine cycle architecture ? two data pointers ? on-chip memory ? 44 kbyte + 4 kbyte flash for program code and data (4 kbyte eepro m emulation built-in) ? 512 byte one time programmable memory (otp) ? 512 byte 100 time programmable memory (100tp) ? 256 byte ram, 3 kbyte xram ? bootrom for startup firm ware and flash routines ? core logic supply at 1.5 v ? on-chip osc and pll for clock generation ? loss of clock detection with fa il safe mode for power switches ? watchdog timer (wdt) with programmabl e window feature for refresh operation and warning prior to overflow ? general-purpose i/o port (gpio) with wake-up capability ? multiplication/division unit (m du) for arithmetic calculation ? software libraries to support floating point and mdu calculations ? five 16-bit timers - timer 0, time r 1, timer 2, timer 21 and timer 3 ? capture/compare unit for pwm signal generation (ccu6) with timer 12 and timer 13 ? full duplex serial interface (uart) with lin support ? synchronous serial channel (ssc) ? on-chip debug support via 2-wir e device access port (dap) ? lin bootstrap loader (lin bsl) ? lin transceiver compliant to lin 1.3, lin 2.0 and lin 2.1 ? 2 x low side switches with clamping capability incl. pwm functionality, e.g. as relay driver ? 2 x high side switches with cyclic sense option and pwm functionality, e.g. for led or powering of switches ? 5 x high voltage monitor input pins for wake-up and with cyclic sense and analog measurement option ? measurement unit with 10 channels, 8-bit a/d converter (adc2) and data post processing ? 8 channels, 10-bit a/d converter (including ba ttery voltage and supply voltage measurement) (adc1) ? single power supply from 3.0 v to 27 v ? low-dropout voltage regulators (ldo) ? dedicated 5 v voltage regulator for external loads (e.g. hall sensor) ? programmable window watchdog (wdt1) with independent on-chip clock source ? power saving modes ? mcu slow-down mode ? stop mode ? sleep mode ? cyclic wake-up and cyclic sense during stop mode and sleep mode ? power-on and undervoltage/brownout reset generator ? overtemperature protection ? overcurrent protection with shutdown ? supported by a full range of development tools including c compilers, macro assembler packages, emulators, evaluation boards, hll debugger, pr ogramming tools, software packages ? temperature range t j : -40 c up to 150 c ? package vqfn-48-29 ? green package (rohs compliant)
TLE9833QX summary of features data sheet 6 rev. 1.1, 2012-03-08 1.1 device types / ordering information the tle983x product family features devices with different pe ripheral modules, configurations and program memory sizes to offer cost-effective solu tions for different application requirements. table 1 describes the TLE9833QX device configuration. table 1 device configuration device name max clock frequency high side switches high voltage monitor inputs flash size bidirectional parallel port i/os operational amplifier TLE9833QX 40 mhz 2 5 48 kbyte 11 no
TLE9833QX summary of features data sheet 7 rev. 1.1, 2012-03-08 1.2 abbreviations the following acronyms and terms are used within this document. list see in table 2 . table 2 acronyms acronyms name alu arithmetic logic unit ccu6 capture compare unit 6 cgu clock generation unit cmu cyclic management unit dap device access port dpp data post processing ecc error correction code eeprom electrically erasable pr ogrammable read only memory gpio general purpose input output fsr full scale range icu interrupt control unit iram internal random access memory - internal data memory ldo low dropout voltage regulator lin local interconnect network lsb least significant bit mcu micro controller unit mdu multiplication division unit mmc monitor mode control msb most significant bit nmi non maskable interrupt ocds on chip debug support otp one time programmable osc oscillator pc program counter pcu power control unit pd pull down pgu power supply generation unit pll phase locked loop pmu power management unit psw program status word pu pull up pwm pulse width modulation ram random access memory rcu reset control unit rmu reset management unit
TLE9833QX summary of features data sheet 8 rev. 1.1, 2012-03-08 rom read only memory sck ssc clock sfr special function register sow short open window (for wdt1) spi serial peripheral interface ssc synchronous serial channel ssu system status unit tms test mode select uart universal asynchronous receiver transmitter udig universal digital controller for adc1 vbg voltage reference band gap wdt watchdog timer wmu wake-up management unit xram on-chip external data memory xsfr on-chip external special function register table 2 acronyms acronyms name
TLE9833QX general device information data sheet 9 rev. 1.1, 2012-03-08 2 general device information 2.1 pin configuration figure 1 TLE9833QX pin configurati on, vqfn-48-29 package (top view) vbatsense 48 vs 47 n.c. 46 vddext 45 vddp 44 gnd 43 vddc 42 p 1.3 /exint1 _1 /cc62_ 0/ ccpos0_ 2/ exf21 _1 39 n.c. 41 n.c. 40 gnd 38 36 p2 .3/ an3/ccpos 1_ 0/e xint0_ 2/ctrap _1/ cc6 0_ 1 13 lsgnd 14 p1 .0/ t0 _1 /cc61_ 0/ sck_1 /exf 21 _3 15 p1.1/t1_1/mtsr_1/t21ex_3/cout61_0 16 p1. 2/exint 0_ 1/t21 _ 1/mrst_1 /ccpos 2_2 /cout63 _0 17 p0. 1/t13 hr_0 /rxd_1 /t2ex _1 /t21 _0 /exint0 _3 18 tms/dap1 19 gnd 20 p0. 0/t12 hr_0 /t2_ 0/dap 0/exint 2_ 3/exf 21 _0 /rxdo 21 reset 22 p0. 2/ctrap_ 0/ t21 ex _0 /exint 1_ 3/txd_ 1/exf 2_ 0 23 p0. 3/sck _0 /exint1 _2 /t0/ ccpos0_ 1/ exf21 _ 2 24 p 0.4 /mtsr_0 /cc60 _ 0/t21 _ 2/exint 2_ 2/ccpos 1_ 1/clkout _0 25 p0.5/mrst_0/exint0_0/t21ex_2/t1/ccpos2_1/cout60_0 26 p1.4/exint2_1/t21ex1/ccpos1_2/clkout_1/cout62_0 27 xtal1 28 xtal2 29 n.c. 30 gnd 31 p 2.5/an5/t1_2 33 adcgnd 34 varef 35 p2.7/an7/ccpos2_0/exint2_0/t13hr_1/cc62_1 32 p 2.4/an4/t0_2 ls2 12 ls1 11 n.c. 10 mo n5 9 mo n4 8 mo n3 7 mo n2 6 mo n1 5 hs2 4 hs1 3 lingnd 2 lin 1 p2. 1/an1 /ccpos0 _0 /exint 1_0 /t12 hr_ 1/ cc61 _1 37
TLE9833QX general device information data sheet 10 rev. 1.1, 2012-03-08 2.2 pin definitions and functions after reset, all pins are configured as input (except supply and lin pins) with one of the following settings: ? pull-up device enabled only (pu) ? pull-down device enabled only (pd) ? input with both pull-up and pull-down devices disabled (i) ? output with output stage deacti vated = high impedance state (hi-z) the functions and default states of the TLE9833QX external pins are provided in the following table. type: indicates the pin type. ? i/o: input or output ? i: input only ? o: output only ? p: power supply table 3 pin definitions and functions symbol pin number type reset state function p0 port 0 port 0 is an 6-bit bidirectional general purpose i/o port. alternate functions can be assigned as follows: dap, ccu6, timer 0, timer 1, timer 2, timer 21, uart, ssc, external interrupt input and clock output. p0.0 20 i/o i/pu t12hr_0 t2_0 dap0 exint2_3 exf21_0 rxdo ccu6 timer 12 hardware run input timer 2 input debug access port 0 external interrupt input 0 timer 21 external flag output uart transmit data output (synchronous mode) p0.1 17 i/o i/pu t13hr_0 rxd_1 t2ex_1 t21_0 exint0_3 ccu6 timer 13 hardware run input uart receive input timer 2 external trigger input timer 21 input external interrupt input 0 p0.2 22 i/o i/pu ctrap_0 t21ex_0 exint1_3 txd_1 exf2_0 ccu6 trap input timer 21 external trigger input external interrupt input 1 uart transmit output timer 2 external flag output p0.3 23 i/o i/pu sck_0 exint1_2 t0 ccpos0_1 exf21_2 ssc clock input (for slave) / output (for master) external interrupt input 1 timer 0 input ccu6 hall input 0 timer 21 external flag output p0.4 24 i/o i/pu mtsr_0 cc60_0 t21_2 exint2_2 ccpos1_1 clkout_0 ssc master transmit output / slave receive input ccu6 capture/compare channel 0 input/output timer 21 input external interrupt input 2 ccu6 hall input 1 clock output
TLE9833QX general device information data sheet 11 rev. 1.1, 2012-03-08 p0.5 25 i/o i/pu mrst_0 exint0_0 t21ex_2 t1 ccpos2_1 cout60_0 ssc master receive input / slave transmit output external interrupt input 0 timer 21 external trigger input timer 1 input ccu6 hall input 2 ccu6 capture/compare channel 0 output p1 port 1 port 1 is an 5-bit bidirectional general purpose i/o port. alternate functions can be assigned as follows: ccu6, timer 0, timer 1 timer 21, ssc, external interrupt input and clock output. p1.0 14 i/o i t0_1 cc61_0 sck_1 exf21_3 timer 0 input ccu6 capture/compare channel 1 input/output ssc clock input (for slave) / output (for master) timer 21 external flag output p1.1 15 i/o i t1_1 mtsr_1 t21ex_3 cout61_0 timer 1 input ssc master transmit out put/slave receive input timer 21 external trigger input ccu6 capture/compare channel 1 output p1.2 16 i/o i exint0_1 t21_1 mrst_1 ccpos2_2 cout63_0 external interrupt input 0 timer 21 input ssc master receive input/slave transmit output ccu6 hall input 2 ccu6 capture/compare channel 3 output p1.3 39 i/o i exint1_1 cc62_0 ccpos0_2 exf21_1 external interrupt input 1 ccu6 capture/compare channel 2 input/output ccu6 hall input 0 timer 21 external flag output p1.4 26 i/o i exint2_1 t21ex_1 ccpos1_2 clkout_1 cout62_0 external interrupt input 2 timer 21 external trigger input ccu6 hall input 1 clock output ccu6 capture/compare channel 2 output p2 port 2 port 2 is an 5-bit general purpose input-only port. alternate functions can be assigned as follows: ccu6, timer 0, timer 1, timer 21 and external interrupt input it is also used as analog inputs for the 10-bit adc (adc1). p2.1 37 i i an1 ccpos0_0 exint1_0 t12hr_1 cc61_1 adc1 analog input channel 1 ccu6 hall input 0 external interrupt input 1 ccu6 timer 12 hardware run input ccu6 capture/compare channel 1 input table 3 pin definitions and functions (cont?d) symbol pin number type reset state function
TLE9833QX general device information data sheet 12 rev. 1.1, 2012-03-08 p2.3 36 i i an3 ccpos1_0 exint0_2 ctrap_1 cc60_1 adc1 analog input channel 3 ccu6 hall input 1 external interrupt input 0 ccu6 trap input ccu6 capture/compare channel 0 input p2.4 32 i i an4 t0_2 adc1 analog input channel 4 timer 0 input p2.5 31 i i an5 t1_2 adc1 analog input channel 5 timer 1 input p2.7 35 i i an7 ccpos2_0 exint2_0 t13hr_1 cc62_1 adc1 analog input channel 7 ccu6 hall input 2 external interrupt input 2 ccu6 timer 13 hardware run input ccu6 capture/compare channel 2 input power supply vs 47 p ? battery supply input vddp 44 p ? i/o port supply (5.0 v). do not connect external loads. for buffer and bypass capacitors. vddc 42 p ? core supply (1.5 v during active mode, 0.9 v during stop mode). do not connect external loads. for buffer/bypass capacitor. vddext 45 p ? external voltage supply output (5.0 v, 20 ma) lsgnd 13 p ? low side ground ls1, ls2 gnd 30, 43, 19, 38 p ? core supply ground; analog supply ground adcgnd 33 p ? analog supply ground for adc1 lingnd 2 p ? lin ground monitor inputs mon1 5 i i high voltage monitor input 1 mon2 6 i i high voltage monitor input 2 mon3 7 i i high voltage monitor input 3 mon4 8 i i high voltage monitor input 4 mon5 9 i i high voltage monitor input 5 high side switch / low side switch outputs ls1 11 o hi-z low side switch output 1 ls2 12 o hi-z low side switch output 2 hs1 3 o hi-z high side switch output 1 hs2 4 o hi-z high side switch output 2 lin interface lin 1 i/o pu lin bus interface input/output table 3 pin definitions and functions (cont?d) symbol pin number type reset state function
TLE9833QX general device information data sheet 13 rev. 1.1, 2012-03-08 others varef 34 i/o o 5v adc1 reference voltage xtal1 27 i i external oscillator input xtal2 28 o hi-z external oscillator output tms 18 i i/pd tms dap1 test mode select input debug access port 1 reset 21 i/o i/o/pu reset input, not available during sleep mode vbat_sense 48 i i battery supply voltage sense input n.c. 10, 29, 40, 41, 46 ? ? not connected - can be connected to gnd table 3 pin definitions and functions (cont?d) symbol pin number type reset state function
TLE9833QX functional description data sheet 14 rev. 1.1, 2012-03-08 3 functional description this highly integrated circuit contains analog and digital functional blocks. for system and interface control an embedded 8-bit state-of-the-art micr ocontroller, compatible to the standard 8051 core with on-chip debug support (ocds), is available. for internal and external power supply purposes, on-chip low drop-out regulators are existent. an internal osc illator provides a cost effectiv e and suitable clock in partic ular for lin slave nodes. as communication interface, a lin transceiver and several high voltage monitor inputs with adjustable threshold and filters are available. furthermore two high side switches (e .g. for driving leds or cyc lic powering of switches), two low side switches (e.g. for relays) and several general purpose input/outputs (gpio) with pulse-width modulation (pwm) capa bilities are available. the micro controller unit (mcu) superv ision and system protection including reset feature is controlled by a programmable window watchdog. a cyclic wake-up circuit, supply voltage supervision and integrated temperature sensors are available on-chip. all relevant modules offer power saving modes in order to support terminal 30 connec ted automotive applications. a wake-up from the power saving mode is possible via a li n bus message, via the monitoring inputs, via the gpio ports or repetitive with a programmable time period (cyclic wake-up). the integrated circuit is available in a vqfn-48-29 package with 0.5 mm pitch and is designed to withstand the severe conditions of automotive applications.
TLE9833QX functional description data sheet 15 rev. 1.1, 2012-03-08 block diagram figure 2 block diagram the TLE9833QX has several operational modes mainly to support low power consumption requirements. the low power modes and state transitions are depicted in figure 3 below. 8 bit - mcu measurement unit xtal2 xtal1 gpio ports 5 v dap 8-ch. 10-bit adc p2.1, p2.3 ? p2.5, p2.7 (an1, an3 ? an5, an7) rc-oszillator 5mhz pll mcu timer 2/21 ccu6 (capture compare unit) ssc (synchr. serial channel) debug (dap) port control mdu (multiply / division unit) scu p0.0 tms wdt vpre vddp vddc power down supply pmu-xsfr xc800 ewarp core timer 0/1 irq pmu/ pcu cgu misc brg lin control misc control power-control vref5v tsense 8-bit adc bg wmu cycmu vbat_sense v b a t _ s e n s e v s _ s e n s e vddp_sense vddc_sense dpp ls1_sense l s 2 _ s e n s e t_sense pwm-unit ts_ls_sense mon1 mon5 rmu pmu lin lingnd ls2 ls1 hs 1 vddext cmu scu_pm ap_sub_ctrl ir clk_gen lsgnd lin transceiver low side 2 mon attenuator vddext vddp vddc wdt1 attenuator vddc_sense rcu vddp_sense vbat_sense vs_sense v m o n 1 . . 5 wake varef adcgnd mux vmon 1...5 vbat_sense vs_sense uart timer 3 vs lp_clk2 100khz wake memories map ram flash-36kb bootrom 256 byte-ram 3kb xram xsfr-bus 0 ref_sense p0.1 ? p0.5 p1.0 ? p1.4 hs 2 high side 1 high side 2 low side 1 2 6 pmu/ pcu 7 trigger ctrl not used 0 1 2 3 5 6 7 8 9 4 lp_clk 20mhz xsfr-bus sfr-bus prewarn_sup_nmi xint . .
TLE9833QX functional description data sheet 16 rev. 1.1, 2012-03-08 figure 3 power control state diagram reset mode the reset mode is a transition mode e.g. during power-up of the device after a power- on reset. in th is mode the on-chip power supplies are enabled and all other modules are initialized. once the co re supply vddc is stable, the active mode is entered. in case the watchdog timer wd t1 fails for more than four times, a fail-safe transition to the sleep mode is done. active mode in active mode all module s are activated and the tle9 833qx is fully operational. stop mode the stop mode is one out of two low power modes. the tr ansition to the low power modes is done by setting the respective bits in the mode contro l register. in stop mode t he embedded microcontroller is still powered allowing faster wake-up reaction times. a wake-u p from this mode is possible by li n bus activity, the high voltage monitor input pins or the re spective 5v gpios. sleep mode the sleep mode is the second low-power mode. the transition to the low-power modes is done by setting the respective bits in the mcu mode cont rol register. in sleep mode the embedded microcontroller power supply is deactivated allowing the lowest system power consumption, but the wake-up time is longer compared to the stop mode. a wake-up from this mode is possible by lin bus ac tivity or the high voltage monitor input pins. a wake- up from sleep mode behaves similar to a power-on reset. safety fallback sleep command sleep mode active mode stop mode stop command transition by software transition by external event lin wake or mon wake lin wake or mon wake or gpio wake power-up vs > 3v cyclic-sense cyclic wake cyclic wake vddc stable & error_supp < 5 vddc fail (error_supp++) wdt1 reset (error_wdt++) safety fallback error_supp = 5 safety fallback error_wdt = 5 transition by internal event cyclic-sense reset pcu_state_diagram_simple_cus.vsd
TLE9833QX functional description data sheet 17 rev. 1.1, 2012-03-08 cyclic wake-up mode the cyclic wake-up mode is a special operating mode of the sleep mode and the stop mode. the transition to the cyclic wake-up mode is done by first setting the respective bits in the mode control regi ster followed by the sleep or stop command. additional to the cyclic wake-up be havior (wake-up after a programmable time period), the wake-up sources of the normal stop mode and sleep mode are available. cyclic sense mode the cyclic sense mode is a special operating mode of th e sleep mode and the stop mode. the transition to the cyclic sense mode is done by first setting the respective bits in the mode cont rol register followed by the stop or sleep command. in cyclic sens e mode a high side switch can be swit ched on periodically for biasing some switches for example. the wake-up condition is configurab le, when the sense result of defined monitor inputs at a window of interest changed compared to the previous wake-up period or reached a defined state respectively. in this case the active mode is entered immediately. for cyclic sense in stop mode vddext can be switched on periodically. furthermore cyclic sense allows to sense ded icated gpio port states and transitions when in stop mode. the following table shows the possible power mode configur ations of each major module or function respectively. table 4 power mode configurations module/function active mode stop mode sleep mode comment vdd1v5pd on on on power down supply vpre, vddp, vddc on on (no dynamic load) off ? vddext on/off on (no dynamic load)/off cyclic on/off off ? hsx on/off cyclic on/off cyclic on/off cyclic sense lsx on/off off off ? pwm gen. on/off off off ? lin trx on/off wake-up only/ off wake-up only/ off ? mon1 - mon5 (wake-up) n.a. disab led/static/cyclic disabled/static/ cyclic cyclic: combined with hs=on mon1 - mon5 (measurement) on/off off off available on four channels vs sense on/off brownout detection brownout detection brownout detection brownout detection done in pcu vbat_sense on/off off off ? gpio 5v (wake-up) n.a. disabled/static/cyclic off ? gpio 5v (active) on on off ? wdt1 on off off ?
TLE9833QX functional description data sheet 18 rev. 1.1, 2012-03-08 wake-up source prioritization all wake-up sources have the same priority. in order to handle the asynchronous nature of the wake-up sources, the first wake-up signal will in itiate the wake-up se quence. nevertheless all wake-up sources are latched in order to provide all wake-up events to the application software. the software can clear the wake-up source flags. it is ensured, that no wake-up event is lost. as default wake-up sources, the lin and mon inputs are activated after power-on reset only. gpio ports as wake- up sources are disabled by default after power-on reset. the application software can reconfigure the wake-up sources according to the application needs. wake-up levels and transitions the wake-up can be triggered by rising, falling or both signal edges for each monito r and gpio input individually. cyclic modes n.a. cyclic wake-up/ cyclic sense/off cyclic wake-up/ cyclic sense/off cyclic sense with hs, vddext; wake-up from cyclic wake needs mc for entering sleep mode / stop mode again measurement unit on 1) off off ? mcu on/slow- down/halt stop 2) off ? clock gen (mc) on off off ? lp_clk (20 mhz) on off off wdt1 lp_clk2 (100 khz) on on on for cyclic wake-up 1) cannot not be switched off due to safety reasons 2) mc pll clock disabled, mc supply reduced to 0.9 v table 4 power mode configurations module/function active mode stop mode sleep mode comment
TLE9833QX functional description data sheet 19 rev. 1.1, 2012-03-08 3.1 power management unit (pmu) the purpose of the power management unit is to ensure the fail safe behavior of embedded automotive systems. therefore the power management unit controls all syst em modes including the corresponding transitions. the power management unit is responsible for generating all required voltage supplies for the embedded mcu (vddc, vddp) and the external sensor supply (vddext). additio nally, the pmu provides well defined sequences for the system mode transitions and generates hierarchical reset priorities. the reset priorities control the reset behavior of all system functionalities, especia lly the reset behavior of the embedded mcu, including the test hardware. all these functions are controlled by fini te state machines. the system master functionality of the pmu forces the generation of an independent logic supply (power down supply) and system clock (lp_clk). therefore the pmu needs a module internal logic supply and system clock which works independently of the mcu clock. the following state diagram shows the available modes of the device. figure 4 power management unit system modes start-up active stop sleep vs > 3v stop command (from mcu) lin-wake | mon-wake | gpio-wake | cyclic _wake | pmu_pin = 1 | sup_tmout = 1 sleep command (from mcu) | wdt1_seq_fail = 1 vddc =stable & error_supp<5 vddc = fail error_sup=5 pmu_pin = 1 | pmu_soft = 1 | (pmu_ext_wdt = 1 & wdt1_seq_fail= 0) lin-wake | mon-wake | cyclic _wake pm u_system _m odes _ cus.vsd
TLE9833QX functional description data sheet 20 rev. 1.1, 2012-03-08 figure 5 power management unit block diagram power management unit power supply generation (psg) hall_supply power down supply vddp vddc vddext pmu-control pmu-xsfr pmu-pcu pmu-wmu pmu-cycmu pmu-cmu pmu-rmu mon 1...5 lin p0.0?.p0.5 p1.0?.p1.4 vs clk_20mhz clk_100khz pheripherals i n t e r n a l b u s
TLE9833QX functional description data sheet 21 rev. 1.1, 2012-03-08 table 5 description of pmu submodules mod. name modules functions power down supply independent supply voltage generation for pmu this supply is only dedicated to the pmu to ensure a independent operation of generated power supplies (vddp, vddc). lp_clk (= 20 mhz) - clock source for all pmu submodules - backup clock source for system - clock source for wdt1 this ultra low power oscillato r generates the clock for the pmu. this clock is also used as backup clock for the system in case of pll clock failure and as independent clock source for wdt1 lp_clk2 (= 100 khz) clock source for pmu this ultra low power oscillator generates the clock for the pmu mainly in stop mode and in the cyclic modes. peripherals peripheral blocks of pmu this blocks includes all relevant peripherals to ensure a stable and fail safe pmu startup and operation power supply generation unit (pgu) voltage regulators for vddp and vddc this block includes the voltage regulators for the pad supply (vddp) and the core supply (vddc) including all diagnosis and safety features vddext (hall sensor supply) voltage regulator for vddext to supply external modules (e.g. hall sensors) this voltage regulator is a dedicated supply for external modules and can also be used for cyclic sense operations (e.g. with hall sensor) pmu-xsfr all pmu relevant extended special function registers this module contains all pmu relevant registers, which are needed to control and monitor the pmu. pmu-pcu power control unit of the pmu this block is responsible for cont rolling all power related actions within the pgu module. pmu-wmu wake-up management unit of the pmu this block is responsible for controlling all wa ke-up related actions within the pmu module. pmu-cycmu cyclic management unit of the pmu this block is responsible for controlling all actions within cyclic mode. pmu-cmu clock management unit of th e pmu this block is responsible for controlling all clocking actions within the pmu. pmu-rmu reset management unit of the pmu this block is responsible for generating all system required resets.
TLE9833QX functional description data sheet 22 rev. 1.1, 2012-03-08 3.1.1 voltage regulator 5.0v (vddp) this module represents the 5 v voltage regulator, which serves as pad supply for the parallel port pins and other 5 v analog functions. features ? 5 v low-drop voltage regulator ? current limitation ? overcurrent monitoring and shutdown with mcu signalling (interrupt) ? overvoltage monitoring with mcu signalling (interrupt) ? undervoltage monito ring with mcu signalling (interrupt) ? preregulator for vddc regulator ?gpio supply ? pull-down current source at the output for sleep mode (100 a) the output capacitor c vddp is mandatory to ensure a proper regulator functionality. figure 6 module block diagram of vddp voltage regulator 5v ldo vddp-5v supervision vs pmu_5v_ov erlo ad pmu_5v_overvolt pmu_5v_overcurr c vs c vddp vddp regulator
TLE9833QX functional description data sheet 23 rev. 1.1, 2012-03-08 3.1.2 voltage regulator 1.5v (vddc) this module represents the 1.5 v voltage regulator, which serves as core supply for the 8-bit c and other chip internal analog 1.5 v functions (e.g. 8 bit adc). to further reduce the current consumption of the 8-bit mcu during stop mode the output voltage is optionally reduced to 0.9 v. features ? 1.5 v low-drop voltage regulator ? optional 0.9 v in stop mode ? current limitation ? overcurrent monitoring and shutdown with mcu signalling (interrupt) ? overvoltage monitoring with mcu signalling (interrupt) ? undervoltage monito ring with mcu signalling (interrupt) ? pull-down current source at the output for sleep mode (100 a) the output capacitor c vddc is mandatory to ensure a proper regulator functionality. figure 7 module block diagram of vddc voltage regulator 1.5 / 0.9v ldo vddc-1.5v supervision vddp-5v pmu_1v5_overload pmu_1v5_overvolt pmu_1v5_overcurr c vddp c vddc vddc regulator
TLE9833QX functional description data sheet 24 rev. 1.1, 2012-03-08 3.1.3 external voltage re gulator 5.0v (vddext) the external voltage regulator provides 5 v output voltag e in order to supply external circuitry like leds, hall sensors or potentiometers. features ? switchable +5 v, 20 ma low-drop voltage regulator ? switch-on overcurrent blanking time in order to drive small capacitive loads ? short circuit robust ? overvoltage monitoring wi th mcu interrupt signalling ? undervoltage monito ring with mcu interrupt signalling ? selectable switch-on slew-rate 0.95 v/s max. @10 ma supply current, 10 nf capacitive load ? pull-down current source at the output for sleep mode and off mode (100 a) ? cyclic sense option together with gpios figure 8 module block diagram vddext ldo vddext-5v supervision vs vddext_overload vddext_overvolt vddext_overcurr c vs c vddext vddext regulator
TLE9833QX functional description data sheet 25 rev. 1.1, 2012-03-08 3.2 system control unit 3.2.1 system control unit - power modules the system control unit of the power modul es consists of the following sub-modules: ? reset control unit (rcu): generati on of all required subsystem resets ? clock generation unit (cgu): providing all required clocks to the analog subsystem ? interrupt control unit (icu ): all system relevant interr upt flags and status flags ? power control unit (pcu): takes over control wh en device enters and exits sleep mode and stop mode ? system status unit (ssu): controls mode changes due to system failures ? external watchdog (wdt1): independent syst em watchdog to monitor system activity figure 9 block diagram of system control unit - power modules system control unit-power modules pcu cgu ssu rcu wdt1 reset_type_0 i n t e r n a l b u s reset_type_1 reset_type_2 reset_type_3 reset_type_4 xsfr-bpi fsys on signals to analog peripherals; status signals from analog peripherals lp_clk mi_clk clk_2mhz xint icu prewarn_sup_nmi all sts bits from analog peripherals
TLE9833QX functional description data sheet 26 rev. 1.1, 2012-03-08 3.2.2 system control unit - digital part the system control unit - digital part supports all central control tasks in the TLE9833QX. it consists of the following submodules: ? clock system and control ? reset control ? power management ? interrupt management ? general port control ? flexible peripheral management ? module suspend control ? watchdog timer ? xram addressing modes ? error detection and corr ection in data memory ? miscellaneous control ? register mapping 3.3 xc800 core the xc800 core is a complete, high performance cpu core that is functionally upward compatible to the 8051. while the standard 8051 core is designed around a 12-cl ock machine cycle, the xc800 core uses a two-clock period machine cycle. the instruction set consists of 45% one-byte, 41% two-by te and 14% three-byte instructions. each instruction takes 1, 2 or 4 machine cycles to execute. in case of access to slower memory, the access time may be extended by wait cycles (one wait cycle lasts one machin e cycle, which is equivalent to two clock cycles). via the dedicated dap interface the xc800 core suppor ts a range of debugging features including basic stop/start, single-step execution, breakpoint support an d read/write access to the data memory, program memory and special function registers. the key features of the xc800 co re implemented are listed below. ? two clocks per machine cycle ? 256 byte of inte rnal data memory ? program memory download option ? 15-source, 4-level interrupt controller ? 2 data pointers ? power saving modes ? dedicated debug mode via low-pin-count dap interface (native jtag mode) ? two 16-bit timers (timer 0 and timer 1)
TLE9833QX functional description data sheet 27 rev. 1.1, 2012-03-08 figure 10 shows the functional blocks of the xc800 core. th e xc800 core consists ma inly of the instruction decoder, the arithmetic section, the program control section, the access control section, and the interrupt controller. the instruction decoder decodes each instruction and ac cordingly generates the internal signals required to control the functions of the individual units within the core . these internal signals have an effect on the source and destination of data transfers and control the alu processing. figure 10 xc800 core block diagram the arithmetic section of the processor performs extensive data manipulation and consists of the arithmetic/logic unit (alu), a register, b register and psw register. t he alu accepts 8-bit data words from one or two sources and generates an 8-bit result under the control of the inst ruction decoder. the alu performs both arithmetic and logic operations. arithmetic operati ons include add, subtract, multiply , divide, increment, decrement, bcd- decimal-add-adjust and compare. logic operations include and, or, exclusive or, complement and rotate (right, left or swap nibble (left four)). also included is a bo olean unit performing the bi t operations as set, clear, complement, jump-if-set, jump-if-not-set, jump-if-set-an d-clear and move to/from carry. the alu can perform the bit operations of logical and or logical or between an y addressable bit (or its complement) and the carry flag, and place the new result in the carry flag. the program control section controls the sequence in which the instructions stored in program memory are executed. the 16-bit program counter (pc) holds the address of the next instru ction to be executed. the conditional branch logic enables internal and external events to the processor to c ause a change in the program execution sequence. the access control unit is responsible for the selection of the on-chip memory resour ces. the interrupt requests from the peripheral units are handled by the interrupt controller unit. register interface alu core sfrs 16-bit registers & memory interface opcode decoder state machine & power saving interrupt controller multiplier / divider opcode & immediate registers timer 0 / timer 1 internal data memory external sfrs external data memory program memory clocks memory wait reset legacy external interrupts (ien0, ien1) external interrupts non-maskable interrupt core block diagram
TLE9833QX functional description data sheet 28 rev. 1.1, 2012-03-08 3.4 memory architecture the TLE9833QX cpu manipulates operands in the following memory spaces: ? 48 kbyte of flash memory in code space ? bootrom memory in code space ? 256 byte of internal ram data memory in internal data space ? 3 kbyte of xram memory in code space and external data space (xram can be read/written as program memory or external data memory) ? 128 byte of special function re gisters sfr in internal data space ? 256 byte of special function regi sters xsfr in external data space. figure 11 illustrates the memory addre ss spaces of the TLE9833QX. figure 11 TLE9833QX memory map special function registers indirect address direct address 80 h ff h 00 h code space external data space internal data space internal ram memory map user mode 40 h 7f h internal ram xram 3 kbyte reserved 2) reserved 2) 0' 0000 h flash lower 32 kbyte boot rom xram 3 kbyte flash upper 16 kbyte 0' 8000 h 1' 0000 h 2' f000 h 2' 0000 h 3' 0000 h 4' 0000 h 5' 0000 h 6' 0000 h 7' 0000 h 8' 0000 h 9' 0000 h a' 0000 h b' 0000 h c' 0000 h d' 0000 h e' 0000 h f' 0000 h f' ffff h bank 1 bank 3 bank 4 bank 5 bank 6 bank 7 bank 8 bank 9 bank b bank c bank d bank e bank 2 bank 0 reserved 1) reserved 1) reserved reserved extension stack ram memory extension stack pointer (mexsp) not user-accessible ; hw access only 80 h ff h 2' fc00 h 2' 8000 h 2' 9c00 h reserved 1) the lower 32 kbyte of the 48 kbyte nvm is always mapped and can be accessed in the lower half (0000 h to 7fff h ) of each bank in the code space (except bank a, where the 3 kbyte xram is mapped.) 2) xram is always mapped and can be accessed in the range (f000 h to fbff h ) of each bank in the external data space; xsfr is always mapped and can be accessed in the range (0000 h to 00ff h ) of each bank in the external data space. flash lower 32 kbyte reserved 2' 0100 h xsfr, 256 byte xram 3 kbyte bank a a' 0c00 h reserved reserved 1) bank f 0' c000 h
TLE9833QX functional description data sheet 29 rev. 1.1, 2012-03-08 3.5 flash memory the flash memory provides an embedded user-programma ble non-volatile memory, allowing fast and reliable storage of user code and data. it is operated from a single 1.5v supply (vddc) from the internal voltage regulator and does not require additional programming or erasing voltage. features ? in-system programming via lin (flash mode) and dap ? error correction code (e cc) for dynamic correction of single bit errors and signalling for double bit failures ? support for aborting erase operation ? program width of 128 byte (page) ? minimum erase width of 128 byte (page) ? 4 byte read access ? read access time: 75 ns ? program time for 1 page: 3 ms ? page erase time: 4 ms 3.6 watchdog timer 1 (wdt1) features ? windowed watchdog timer with programmable timing in active mode ? long open window (80ms) after power-up, reset, wake-up ? short open window (30ms) to facilitate flash programming ? disabled during debugging ? safety shutdown to sleep mode after 5 missed wdt1 services there are two watchdog timers in the system. the watchdog timer (wdt) within the microcontroller (see chapter 3.7 ) and the watchdog timer 1 (wdt1), which is described in this section. in active mode, the wdt1 acts as a windowed watchdog timer, which provides a high ly reliable and safe way to recover from software or hardware failures. the wdt1 is always enabled in active mode. in sleep mode, stop mode and ocds mode the wdt1 is disabled. the behavior of the watchdog timer 1 in active mode is depicted in figure 12 .
TLE9833QX functional description data sheet 30 rev. 1.1, 2012-03-08 figure 12 watchdog timer 1 behavior trigger always timeout reset reset reset trigger sow trigger sow trigger timeout or trigger in closed window reset power-up timeout long open window normal ?windowed? operation short open window trigger maximum number of sow triggers exceeded trigger sow
TLE9833QX functional description data sheet 31 rev. 1.1, 2012-03-08 3.7 watchdog timer (wdt) the watchdog timer (wdt) is a sub-module in the system control unit (scu). the watchdog timer provides a highly reliable and secure way to detect and recover from software or hardware failures. the wdt helps to abort an accidental malfunction of the tl e9833qx in a user-specified time pe riod. when enabled, the wdt will cause the TLE9833QX system to be reset if the wdt is not se rviced within a user-programmable time period. the cpu must service the wdt within this time interval to prevent the wdt from causing an TLE9833QX system reset. hence, routine service of the wdt confirms that the system is functioning properly. the wdt is disabled by default. in debug mode, the wdt is suspended by default and stops counting (its debug suspend bit is set by default i.e. modsusp.wdtsusp = 1). therefore during debugging, there is no need to refresh the wdt. features ? 16-bit watchdog timer ? programmable reload value for upper 8 bits of timer ? programmable window boundary ? selectable input frequency of f pclk /2 or f pclk /128 the watchdog timer is a 16-bit timer, wh ich is incremented by a count rate of f pclk /2 or f pclk /128. this 16-bit timer is realized as two concatenated 8-bit timers. the up per 8 bits of the watchdog timer can be preset to a user- programmable value via a watchdog service access in order to vary the watchdog expiring time. the lower 8 bits are reset on each service access. figure 13 shows the block diagram of the watchdog timer unit. figure 13 wdt block diagram wdtrel mux wdt low byte 1:2 clear wdt control 1:128 wdt high byte wdtto wdtin f pclk logic enwdt enwdt_p wdtrst overflow/time-out control & window-boundary control winbcnt
TLE9833QX functional description data sheet 32 rev. 1.1, 2012-03-08 3.8 interrupt system the TLE9833QX supports 14 interrupt vectors with four pr iority levels. eleven of these interrupt vectors are assigned to the on-chip peripherals: timer 0, timer 1, uart, ssc and a/d converter are each assigned to one dedicated interrupt vector; while timer2, timer21, mdu, lin and the capture/compare unit share six interrupt vectors. two interrupt vectors are assigned to the external interrupts. external interrupts 0 to 1 are each assigned to one dedicated interrupt vector, external interrupt 2 shares on interrupt vector with timer21 and the mdu. one interrupt vector is dedicated to the xint interrupt even ts whose interrupt flags are also located in registers in xsfr area. a non-maskable interrupt (nmi) with the high est priority is shared by the following: ? watchdog timer, warning before overflow ? mi_clk watchdog timer overflow event ? pll, loss of lock ? flash, on operation complete, e.g. erase. ? ocds, on user iram event ? oscillator watchdog detection for too low oscillation of f osc ? flash map error ? uncorrectable ecc error on flash, xram and iram ? vsup supply pre warning when any supply voltage drops below or exceeds any threshold. figure 14 , figure 15 , figure 16 , figure 17 and figure 18 give a general overview of the interrupt sources and nodes, and their corresponding control and status flags. figure 19 gives the corresponding overview for the nmi sources.
TLE9833QX functional description data sheet 33 rev. 1.1, 2012-03-08 figure 14 interrupt request sources (part 1) highest lowest priority level bit-addressable request flag is cleared by hardware 000b h et0 ien0.1 tf0 tcon.5 timer 0 overflow 001b h et1 ien0.3 tf1 tcon.7 timer 1 overflow ip.1/ iph.1 ip.3/ iph.3 0023 h es ien0.4 ip.4/ iph.4 >=1 ri scon.0 ti scon.1 uart transmit 0003 h ex0 ien0.0 ie0 tcon.1 ip.0/ iph.0 0013 h ip.2/ iph.2 it0 tcon.0 ex1 ien0.2 ie1 tcon.3 it1 tcon.2 ien0.7 ea p o l l i n g s e q u e n c e uart receive exint0 exicon0.0/1 eint0 exint1 exicon0.2/3 eint1 scon1.1 tien scon1.0 rien
TLE9833QX functional description data sheet 34 rev. 1.1, 2012-03-08 figure 15 interrupt request sources (part 2) highest lowest priority level bit- addressable request flag is cleared by hardware 002b h ip.5/ iph.5 p o l l i n g s e q u e n c e 0033 h eadc ien1.0 ip1.0/ iph1.0 >=1 adcsr0 ircon1.3 adc service request 0 adc service request 1 adcsr1 ircon1.4 et2 ien0.5 >=1 tf2 t2_t2con.7 timer 2 overflow ien0.7 ea >=1 eofsyn linst.4 end of synch byte errsyn linst.5 synch byte error >=1 linst.6 synen t2_t2con1.1 tf2en exf2 t2_t2con.6 exen2 t2_t2con.3 t2ex edges el t2_t2mod.5 t2_t2con1.0 exf2en
TLE9833QX functional description data sheet 35 rev. 1.1, 2012-03-08 figure 16 interrupt request sources (part 3) highest lowest priority level bit- addressable request flag is cleared by hardware p o l l i n g s e q u e n c e 003b h essc ien1.1 ip1.1/ iph1.1 >=1 tir ircon1.1 rir ircon1.2 eir ircon1.0 ssc_eir ssc_tir ssc_rir ien0.7 ea 0043 h ip1.2/ iph1.2 exint2 exicon0.4/5 exint2 ircon0.2 eint2 ex2 ien1.2 irdy mdustat.0 mdu_0 mdu_1 ierr mdustat.1 >=1 tf2 t21_t2con.7 exf2 t21_t2con.6 timer 21 overflow exen2 t21_t2con.3 t21ex edges el t21_t2mod.5 >=1 eiren tiren riren modien.0 modien.2 modien.1 t21_t2con1.1 tf2en t21_t2con1.0 exf2en mducon.7 ie mducon.7 ie
TLE9833QX functional description data sheet 36 rev. 1.1, 2012-03-08 figure 17 interrupt request sources (part 4) figure 18 interrupt request sources (part 5) ien0.7 highest lowest priority level bit-addressable p o l l i n g s e q u e n c e ea 004b h exm ien1.3 ip1.3/ iph1.3 >=1 xinty xintyen xsfrs.t xintyf xsfru.v xintx xintxen xintxf xsfrc.d . . . xsfra.b xintw xintzen xsfri.j xintwf xsfre.f xintz xintzf xsfrg.h >=1 . . . highest lowest priority level p o l l i n g s e q u e n c e ien0.7 bit-addressable request flag is cleared by hardware ea 0053 h ccu6 node 0 ip1.4/ iph1.4 005b h ip1.5/ iph1.5 0063 h ip1.6/ iph1.6 006b h ip1.7/ iph1.7 eccip0 ien1.4 eccip1 ien1.5 eccip2 ien1.6 eccip3 ien1.7 ccu6 node 1 ccu6 node 2 ccu6 node 3 ccu6sr0 ircon3.0 ccu6sr1 ircon3.4 ircon4.0 ccu6src3 ircon4.4 ccu6sr2
TLE9833QX functional description data sheet 37 rev. 1.1, 2012-03-08 figure 19 non-maskable interrupt request source >=1 0073 h nmiwdt nmicon.0 watchdog timer overflow >=1 non maskable interrupt nmipll nmicon.1 pll loss -of-lock nminvm nmicon.2 flash operation complete nmiowd nmicon.4 oscillator watchdog nmiocds nmicon.3 fnmiwdt nmisr.0 fnmipll nmisr.1 fnminvm nmisr.2 fnmiowd nmisr.4 fnmiocds nmisr.3 nmimap nmicon.5 flash map error fnmimap nmisr.5 nmiecc nmicon.6 flash uncorrectable ecc error fnmiecc nmisr.6 nmisup nmicon.7 supply prewarning (type interrupt structure 1 ) fnmisup nmisr.7 fnmirr mmicr.2 iram read event* mmicr.0 nmirre fnmirw mmicr.3 iram write event* mmicr.1 nmirwe * includes other pre-condition >=1 mi_clk watchdog timer overflow (type inter r upt str uctur e 1 ) >=1 xrdbe edcstat.0 edccon.0 xrie irdbe edcstat.1 edccon.1 irie xram uncorrectable ecc error iram uncorrectable ecc error nvmdbe edcstat.2 edccon.2 nvmie
TLE9833QX functional description data sheet 38 rev. 1.1, 2012-03-08 3.9 multiplication/division unit the multiplication/division unit (mdu) prov ides fast 16-bit multiplic ation, 16-bit and 32-bit division as well as shift and normalize features. it has been integrated to support the TLE9833QX core in real-time control applications, which require fast mathematical computations. features ? fast signed/unsigned 16-bit multiplication ? fast signed/unsigned 32-bit divide by 16 -bit and 16-bit divide by 16-bit operations ? 32-bit unsigned normalize operation ? 32-bit arithmetic/logical shift operations 3.10 parallel ports the TLE9833QX has 16 port pins organized into three parallel ports: port 0 (p0), port 1 (p1) and port 2 (p2). each port pin has a pair of internal pull-up and pull-down devi ces that can be individually enabled or disabled. p0 and p1 are bidirectional and can be used as general purpose input/output (gpio) or to perform alternate input/output functions for the on-chip peripherals. when configured as an output, the open drain mode can be selected. bidirectional port features (p0, p1) ? configurable pin direction ? configurable pull-up/ pull-down devices ? configurable open drain mode ? configurable drive strength ? transfer of data through digital inputs and outputs (general purpose i/o) ? alternate input/output for on-chip peripherals
TLE9833QX functional description data sheet 39 rev. 1.1, 2012-03-08 figure 20 general structure of a bidirectional port pin od open drain contr ol register data data register internal bus altdataout 3 altdataout 2 altsel0 alter nate select register 0 altsel1 alter nate select register 1 altdatain pin puden pull -up /pull -down enable register dir direction register pudsel pull -up /pull -down select register pull-up /pull-down contr ol logic altdataout1 pad out in pull device output driver input driver 11 10 01 00 schmitt trigger analogin px_pocony port output driver control registers tccr temper atur e compensation contr ol register
TLE9833QX functional description data sheet 40 rev. 1.1, 2012-03-08 figure 21 shows the structure of an input-only port pin. each p2 pin can only function in input mode. register p2_dir is provided to enable or disable the input driver. wh en the input driver is enabl ed, the actual voltage level present at the port pin is translated into a logic 0 or 1 via a schmitt-trigger device and can be read via register. each pin can also be programmed to activate an internal weak pull-up or pull-down device. the analog input (analog in) bypasses the digital circuitry and schmitt-tri gger device for direct feed-through to the adc1 input channel. figure 21 general structure of an input port pin data dat a regist er internal bus altdatain pin puden pull-up/pull-down enable regist er pudsel pull-up/pull-down select register pull-up/ pull-down cont rol logic pad in pull device input dri ver schmitt trigger analogin
TLE9833QX functional description data sheet 41 rev. 1.1, 2012-03-08 3.11 timer 0 and timer 1 timer 0 and timer 1 can function as bo th, timers or counters. when function ing as a timer, timer 0 and timer 1 are incremented with every machine cycle, i.e. every 2 inpu t clocks (or 2 pclks). when functioning as a counter, timer 0 and timer 1 are incremented in response to a 1-to-0 transition (falling edge) at its respective external input pins, t0 or t1. timer 0 and timer 1 are fully compatible and can be configured in four different operating modes to use in a variety of applications, see table 6 . in modes 0, 1 and 2, the two timers operate independently, but in mode 3, their functions are specialized. table 6 timer 0 and timer 1 modes mode operation 0 13-bit-timer the timer is essentially an 8-bit counter with a divide-by-32 prescaler. this mode is included solely for compatib ility with intel 8048 devices. 1 16-bit-timer the timer registers, tlx and thx, are concatenated to form a 16-bit counter. 2 8-bit timer with auto-reload the timer register tlx is reloaded with a user -defined 8-bit value in thx upon overflow. 3 timer 0 operates as two 8-bit timers the timer registers, tl0 and th0, operate as two separate 8-bit counters. timer 1 is halted and retains its count even if enabled.
TLE9833QX functional description data sheet 42 rev. 1.1, 2012-03-08 3.12 timer 2 and timer 21 timer 2 and timer 21 are 16-bit general purpose timers that are fully compatible and have two modes of operation, a 16-bit auto-reload mode and a 16-bit one channel capture mode, see table 7 . as a timer, the timers count with an input clock of pclk/12 (if prescaler is disabled). as a counter, they count 1-to-0 transitions on pin t2. in the counter mode, the maximum resolution for the count is pclk/24 (if prescaler is disabled). table 7 timer 2 modes mode description auto-reload up/down count disabled ? count up only ? start counting from 16-bit re load value, overflow at ffff h ? reload event configurable for trigger by overflow condition only, or by negative/positive edge at input pin t2ex as well ? programmable reload value in register rc2 ? interrupt is generated with reload events. auto-reload up/down count enabled ? count up or down, direction determined by level at input pin t2ex ? no interrupt is generated ? count up ? start counting from 16-bit re load value, overflow at ffff h ? reload event triggered by overflow condition ? programmable reload value in register rc2 ? count down ? start counting from ffff h , underflow at value defined in register rc2 ? reload event triggered by underflow condition ? reload value fixed at ffff h channel capture ? count up only ? start counting from 0000 h , overflow at ffff h ? reload event triggered by overflow condition ? reload value fixed at 0000 h ? capture event triggered by falling/rising edg e at pin t2ex ? captured timer value stored in register rc2 ? interrupt is generate with reload or capture event
TLE9833QX functional description data sheet 43 rev. 1.1, 2012-03-08 3.13 timer 3 timer 3 can function as timer or counter. when function ing as a timer, timer 3 is incremented in periods based on the system clock. when functioning as a counter, timer 3 is incremented in response to a 1-to-0 transition (falling edge) at its respective input. timer 3 can be config ured in four different operat ing modes to use in a variety of applications, see table 8 . table 8 timer 3 modes mode sub-mode operation 0 - 13-bit timer the timer is essentially an 8-bit counter with a divide-by-32 prescaler. this mode is included solely for compatib ility with intel 8048 devices. 1 a 16-bit timer the timer registers, tlx and thx, are c oncatenated to form a 16-bit counter. 1 b 16-bit timer the timer registers, tlx and thx, are concat enated to form a 16-bit counter, which is triggered by the pwm unit to enable a single shot measurement on a preset channel with the measurement unit. 1 c 16-bit timer the timer registers, tlx and thx, are concat enated to form a 16-bit counter, which is triggered by the pwm unit to enable the lin baudrate measurement. 2 - 8-bit timer with auto-reload the timer register tlx is reloaded with a user-defined 8-bit value in thx upon overflow. 3 a timer 3 operates as two 8-bit timers the timer registers, tl3 and th3, operate as two separate 8-bit counters. 3 b timer 3 operates as two 8-bit timers the timer registers, tl3 and th3, operate as two separate 8-bit counters. in this mode the 100 khz low power clock can be measured. tl 3 acts as an edge counter for the clock edges and th3 as an counter which counts the time between the edges.
TLE9833QX functional description data sheet 44 rev. 1.1, 2012-03-08 3.14 capture/compare unit 6 (ccu6) the ccu6 unit is made up of a timer t12 block with three capture/compare channels and a timer t13 block with one compare channel. the t12 channels can independently generate pwm signals or accept capture triggers, or they can jointly generate control signal pa tterns to drive ac-motors or inverters. a rich set of status bits, synchronized updating of paramet er values via shadow regist ers, and flexible generation of interrupt request signals provide means for efficient software-control. note: the capture/compare module itself is named ccu6 (capture/compare unit 6). a capture/compare channel inside this module is named cc6x. timer 12 block features ? three capture/compare channels, each channel can be used either as capture or as compare channel ? generation of a three-phase pwm supported (six outp uts, individual signals for high side and low side switches) ? 16-bit resolution, maximum count frequency = peripheral clock ? dead-time control for each channel to av oid short-circuits in the power stage ? concurrent update of t12 registers ? center-aligned and edge-aligned pwm can be generated ? single-shot mode supported ? start can be controlled by external events ? capability of counti ng external events ? multiple interrupt request sources ? hysteresis-like control mode timer 13 block features ? one independent compare channel with one output ? 16-bit resolution, maximum count frequency = peripheral clock ? concurrent update of t13 registers ? can be synchronized to t12 ? interrupt generation at period-match and compare-match ? single-shot mode supported ? start can be controlled by external events ? capability of counti ng external events
TLE9833QX functional description data sheet 45 rev. 1.1, 2012-03-08 additional specific functions ? block commutation for brushless dc-drives implemented ? position detection via hall sensor pattern ? noise filter supported for position input signals ? automatic rotational speed measurement an d commutation control for block commutation ? integrated error handling ? fast emergency stop without cpu load via external signal (ctrap ) ? control modes for multi-channel ac-drives ? output levels can be selected and adapted to the power stage the timer t12 can work in capture and/or compare mode fo r its three channels. the modes can also be combined (e.g. a channel works in compare mode, whereas another channel works in capture mode). the timer t13 can work in compare mode only. the multi-channel control unit generates output patterns which can be modulated by t12 and/or t13. the modulation sources can be sele cted and combined for the signal modulation. figure 22 ccu6 block diagram ccu6 module kernel ccu6_mcb05506 + input / output control port control compare compare 22 compare ou tpu t select 3 hall input ou tpu t select 1 trap input 3 capture t13 cc63 start 2 1 compare multi- channel control trap control dead- time control cc60 cc61 compare 1 1 1 t12 cc62 cout60 cout63 t1 3h r t1 2h r cc p os0 cc p os1 cc p os2 ct r ap clock control interrupt control f cc 6 sr[3:0] cc61 cout61 cc62 cout62 cc 6 0 debug suspend t13susp t12 su sp
TLE9833QX functional description data sheet 46 rev. 1.1, 2012-03-08 3.15 uart the uart provides a full-duplex asynchronous rece iver/transmitter, i.e. it can transmit and receive simultaneously. it is also receive-buff ered, i.e. it can commence reception of a second byte before a previously received byte has been read fr om the receive register . however, if the first byte st ill has not been read by the time reception of the second byte is comple te, one of the bytes will be lost. the seri al port receive and transmit registers are both accessed at special function register (sfr) sbuf. writing to sbuf loads the transmit register, and reading sbuf accesses a physica lly separate receive register. uart features ? full-duplex asynchronous modes ? 8-bit or 9-bit data frames, lsb first ? fixed or variable baud rate ? receive buffered ? multiprocessor communication ? interrupt generation on the completion of a data transmission or reception ? baud-rate generator with fractional divider for generating a wide range of baud rates ? hardware logic for break and synch byte detection uart modes the uart can be used in four different modes. in mode 0, it operates as an 8-bit shift register. in mode 1, it operates as an 8-bit serial port. in m odes 2 and 3, it operates as a 9-bit serial port. the only difference between mode 2 and mode 3 is the baud rate, which is fixed in mode 2 but variable in mode 3. the variable baud rate is set by the underflow rate on the dedicated baud-rate generator. the different modes are selected by setting bits sm0 and sm1 to their corresponding values, as shown in table 9 . table 9 uart modes sm0 sm1 operating mode baud rate 0 0 mode 0: 8-bit shift register f pclk /2 0 1 mode 1: 8-bit shift uart variable 1 0 mode 2: 9-bit shift uart f pclk /64 1 1 mode 3: 9-bit shift uart variable
TLE9833QX functional description data sheet 47 rev. 1.1, 2012-03-08 3.16 lin transceiver the lin module is a transceiver for the local interconnect network (lin) compliant to the standards lin 1.3, lin 2.0 and lin 2.1. it operates as a bus driver between th e protocol controller and the physical network. the lin bus is a single wire, bi-directional bus typically used fo r in-vehicle networks, using baud rates between 2.4 kbps and 20 kbps. additionally baud rates up to 40 kbaud are implemented. the lin module offers several different operation modes, including a sleep mode and the normal operation mode. the integrated slope control allows to use several data transmission rates with optimized emc performance. for data transfer at the end of line, a flash mode up to 115 kbaud is also implemented. figure 23 lin transceiver block diagram 3.17 high-speed synchr onous serial interface the high-speed synchronous serial interface (ssc ) supports full-duplex and half-duplex synchronous communication. the serial clock signal can be generated by the ssc internally (master mode), using its own 16- bit baud-rate generator, or can be received from an external master (slave mode). data width, shift direction, clock polarity and phase are programmable. this allows co mmunication with spi-compatible devices or devices using other synchronous serial interfaces. features ? master and slave mode operation ? full-duplex or half-duplex operation ? transmit and receive buffered ? flexible data format transmitter driver + curr. limit . + tsd lin transceiver sleep comparator gnd_lin rxd receiver vs status txd lin_wake 30 k xsfr lin-fsm lin ctrl status filter filter ctrl gnd_lin
TLE9833QX functional description data sheet 48 rev. 1.1, 2012-03-08 ? programmable number of data bits: 2 to 8 bits ? programmable shift direction: lsb or msb shift first ? programmable clock polarity: idle low or high state for the shift clock ? programmable clock/data phase: data shift with leading or trailing edge of the shift clock ? variable baud rate ? compatible with serial peripheral interface (spi) ? interrupt generation ? on a transmitter empty condition ? on a receiver full condition ? on an error condition (receive, phase, baud rate, transmit error) data is transmitted or received on lines txd and rxd, which are normally connected to the pins mtsr (master transmit/slave receive) and mrst (mast er receive/slave transmit). the clo ck signal is output via line ms_clk (master serial shift clock) or input via line ss_clk (slave serial shift clo ck). both lines are normally connected to the pin sclk. transmission and reception of data are double-buffered. figure 24 shows all functional relevant interf aces associated with the ssc kernel. figure 24 ssc interface diagram eir tir cloc k control address decoder mtsr mrsta port control rir ssc module ( kernel ) sl ave ma s t er sl ave f hw _clk f cfg_ clk mrstb mrst mtsra mtsrb sclk sclka sclkb ma s t er interrupt control module product interface bpi interface
TLE9833QX functional description data sheet 49 rev. 1.1, 2012-03-08 3.18 measurement unit the measurement unit is a functional unit that comprises the following associated sub-modules: ? 1 x 8 bit adc (adc2) with 10 inputs. 5 are for single end ed input signals and 5 are for differential input signals. ? monitoring inputs voltage attenuator s with two selectable attenuation setti ngs: divide by 4 and divide by 6 ? supply voltage attenuator s with attenuation of vbat_sense, vs, vddp and vddc. ? vbg monitoring of 8-bit adc (adc2) to guarantee functional safety requirements. ? low side switch current sensing of ls1 and ls 2. allows a scalable overcurrent pre warning. ? temperature sensor for monitoring the chip temperature and low side switches temperature. ? supplement block with reference voltage generation, bias current generation, voltage buffer for flash reference voltage, voltage buffer for analog module reference voltage and test interface. the structure of the measurement functions module is shown in figure 29 . table 10 measurement functions and associated modules module name modules functions central functions unit bandgap reference circuit the bandgap-reference sub-module provides two reference voltages 1. a trimmable reference voltage for the 8-bit adc. a local dedicated bandgap circuit is implemented to avoid deterioration of the referenc e voltage arising e.g. from crosstalk or ground voltage shift. 2. the reference voltage for the flash module 8-bit adc (adc2) 8-bit adc module with 10 multiplexed inputs 1. 5 single-ended inputs 0 ... 1.23v 2. 5 differential inputs 0 ... 1.23v (allocation see follo wing overview figure) 10-bit adc (adc1) 10-bit adc module including analog test bus interface - part of c subsystem 1. vbat_sense measurement on channel 0 of adc1. 2. vs measurement on channel 2 of adc1. 3. monx measurement on channel 6 of adc1. 4. 5 additional (5v) analog inputs from port 2. supply voltage attenuator resistive supply voltage attenuator scales down the supply voltages of the system to the input voltage range of adc1 and adc2. monitoring input attenuator resistive attenuator for (hv) scales down 5 monitoring input voltages to the input voltage range of the adc1. central temperature - low side switch temperature sensor temperature sensor readout with two multiplexed ? v be sensing elements generates outputs voltage which is a linear function of the local chip (junction) temperature. measurement core module digital signal processing and adc control unit 1. generates the control signal for the 8-bit adc2 and the synchronous clock for the switched capacitor circuits, 2. performs digital signal processing functions and provides status outputs for interrupt generation.
TLE9833QX functional description data sheet 50 rev. 1.1, 2012-03-08 figure 25 TLE9833QX meas urement unit-overview measurement -unit measurement core 10 bit adc + udig mux ch8 ch7 ch6 ch5 ch4 ch3 ch2 ch1 ch0 ch9 a d vbat_sense vs vddp vddc low side 1 low side 2 tsense 1 tsense 2 mux ch6 ch5 ch4 ch3 ch2 ch1 ch0 ch7 vref a d udig / 10 m u x / 8 dpp 1. 23 v mon1 mon2 mon3 mon4 mon5 p2.1 p2.3 p2.4 varef p2.5 p2.7 * 0.063 vbg * 0.063 * 0.2 * 0.687 sfr xsfr * 0.252 * 0.252 5 v n.u. * 0 ,25 ( 0,166 ) * 0 ,25 ( 0,166 ) * 0 ,25 ( 0,166 ) * 0 ,25 ( 0,166 ) * 0 ,25 ( 0,166 ) adc 1 adc 2
TLE9833QX functional description data sheet 51 rev. 1.1, 2012-03-08 3.19 measurement core module (incl. adc2) the basic function of this block is the digital postproces sing of several analog digi tized measurement signals by means of filtering, level comparison and interrupt generation. the measurement postprocessing block is built of ten identical channel units at tached to the outputs of the 10-channel 8- bit adc (adc2). it processes ten channels, where the channel sequence and prioritization is programmable within a wide range. features ? 10 individually programmable channels split into two gr oups of user configurable and non user configurable ? individually programmable channel prioritization scheme for measurement unit ? two independent filter stages with programmable low- pass and time filter characteristics for each channel ? two channel configurations: ? programmable upper- and lower trigger thresholds comprising a fully programmable hysteresis ? two individually programmable trigger th resholds with limit hysteresis settings ? individually programmable interrupts and status for all channel thresholds figure 26 measurement core module block diagram digital signal processing 1st order iir mux vbat_sense vs vddp vddc vbg ls1 ts1 ls2 ts2 n.u. ch8 ch7 ch6 ch5 ch4 ch3 ch2 ch1 ch0 ch9 vref calibration unit: y= a + (1+b)*x + - + - th_up_chx th_low_chx / channel controller (sequencer) mux_sel<3:0> a d up_x_sts low_x_sts 4 / 8 + / - + / - tsense tsense_sel / 8 / 8 / 1 / 1 adc2 adc2 - xsfr
TLE9833QX functional description data sheet 52 rev. 1.1, 2012-03-08 3.20 analog digital converter (adc1) the TLE9833QX includes a high-performance 10-bit analog -to-digital converter (adc 1) with eight multiplexed analog input channels. the adc1 uses a successive approx imation technique to convert the analog voltage levels from up to eight different sources. the analog input channe ls of the adc1 are availabl e at an1, an3 - an5, an7. features ? successive approximation ? 8-bit or 10-bit resolution ? 8 analog channels ? four independent result registers ? result data protection for slow cpu access (wait-for-read mode) ? single conversion mode ? autoscan functionality ? limit checking for conversion results ? data reduction filter (accumulation of up to 2 conversion results) ? two independent conversion request sources with programmable priority ? selectable conversion request trigger ? flexible interrupt generation with configurable service nodes ? programmable sample time ? programmable clock divider ? cancel/restart feature for running conversions ? integrated sample and hold circuitry ? compensation of offset errors ? low power modes
TLE9833QX functional description data sheet 53 rev. 1.1, 2012-03-08 3.21 high voltag e monitor input this module is dedicated to monitor external voltage levels above or below a specified threshold or it can be used to detect a wake-up event at each high- voltage mon_in pin in low-power mode. each input is sensitive to an input level monitoring. it is available when the module is switched to active mode via the mon_int (internal signal name) output with a small filter delay of typical 2 s. features ? high-voltage input with v s /2 threshold voltage ? edge sensitive wake capability for power saving modes ? level sensitive wake-up feature configurable for transiti ons from low to high, high to low or both directions ? mon inputs can also be evaluated with adc1 in active mode, using adjustable threshold values (see also chapter 3.20 ). figure 27 monitoring input block diagram monx vs mon_int filter monx logic xsfr
TLE9833QX functional description data sheet 54 rev. 1.1, 2012-03-08 3.22 high side switches the high side switches are intended for resistive load connections (only small line inductance are allowed) leaving the ecu board. typical applications are single or mu ltiple leds of a dashboard or switch illumination or other loads that require a high side switch. a cyclic switch activation during sleep mode or stop mode of the system is also available. features ? multi purpose high side switch fo r resistive load connections (only small line inductan ces are allowed) ? over-current detection with thresholds: 8 ma (also used for on-state open load detection), 50 ma, 100 ma, 150 ma ? cyclic switch activation in sleep mo de and stop mode for cyclic sense su pport with reduced driver capability: max. 40 ma ? open load detection in off mode with two different threshol ds: ground (0 v, for functional safety) and 0.67 * v s ? off-state open load detection operates with two different test currents: 75 a and 750 a ? pwm capability up to 25 khz (with disabled slew rate control only) ? robust output for off ecu connection ? slew rate control ? selectable pwm source: pwm-unit or ccu6 figure 28 high side switch module block diagram high side driver oc-detection ol-detection cyclic- driver xsfr 8 ma 50 ma 100 ma 150 ma 0.67*vs 0v on octh_sel olth_sel vs hs 6.8 nf
TLE9833QX functional description data sheet 55 rev. 1.1, 2012-03-08 3.23 low side switches the general purpose low side switches are intended to cont rol an on-board relay. they include an over-current detection function.the module is designed for on-board connections. features ? multi purpose low side switch ? configurable over-current protection with automatic shutdown ? configurable over-temperature protection with automatic shutdown ? intended for relay driver ? pwm relay driver ? simple relay driver ? integrated clamping ? pwm capability up to 25 khz ? selectable pwm source: pwm-unit or ccu6 figure 29 module block diagram low side driver oc-detection clamp xsfr 250 ma on ls lsgnd
TLE9833QX functional description data sheet 56 rev. 1.1, 2012-03-08 3.24 pwm generator the pwm generator provides up to two configurable pwm channels in order to drive the low side switches ls1, ls2 and the high side switches hs1 and hs2 in a pwm mode. features ? programmable modulation frequency per channel ? programmable duty-cycle per channel with glitch-free reprogramming ? pwm frequency up to 25 khz ? duty-cycle resolution from 0 % ... 100 % in steps of 0.5 % figure 30 module block diagram of pwm module and included pwm switching matrix mod_pwm pwm 1 pwm2 timer 3 xsfr 0 1 2 3 to_trinp_sel ext_int_o ccu6_int_o 0 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3 hs2_pwm__o hs1_pwm_o ls2_pwm_o ls1_pwm_o 0 1 ap_t2ex__o 0 1 ap_t21ex__o ccu6_ch0__o ccu6_ch1__o
TLE9833QX functional description data sheet 57 rev. 1.1, 2012-03-08 3.25 debug system the on-chip debug support (ocds) provides the basi c functionality required for software development and debugging of xc800 based systems.the ocds design is based on the following principles: ? use the built-in debug functionality of the xc800 core ? add a minimum of hardware overhead ? provide support for most of the operations by a monitor program ? use standard interfaces to communicate with the host (a debugger) features ? set breakpoints on instruction address and on address range within the program memory ? set breakpoints on internal ram address range ? support unlimited amount of software breakpoints in flash / ram code region ? step through the program code the monitor mode control (mmc) block at the center of the ocds system brings together control signals and supports the overall functionality. the mmc communi cates with the xc800 core, primarily via the debug interface, and also receives reset and clock signals. a fter processing memory address and control signals from the core, the mmc provides proper access to the dedic ated extra-memories: a monitor rom (holding the code) and a monitor ram (for work data and monitor stack). th e ocds system is accessed through the dap, which is an interface dedicated exclusively for te sting and debugging activiti es and is not normally used in an application. the dedicated tms pin is used for extern al configuration and debugging control. note: all the debug functionality described here can norm ally be used only after TLE9833QX has been started in ocds mode.
TLE9833QX application information data sheet 58 rev. 1.1, 2012-03-08 4 application information 4.1 electric drive application figure 31 shows the TLE9833QX in an electric drive applicat ion setup controlling a dc-brush motor. the two low side switches are controlling a relay eac h. an external fet allows to co ntrol the window lift motor with a pwm signal as generated with the ccu6 module of the microcontroller. note: the following information is given as a hint for the implementation of the device only and shall not be regarded as a description or warranty of a certain functionality, condition or quality of the device. figure 31 simplified application diagram gnd vs vddp lin hs ccpos0 ls1 vddc ls2 pwm mon1 mon2 mon5 mon4 mon3 v bat m double hall sensor e.g. tle4966 vddext ccpos1 direction speed vbat_sense lin gnd
TLE9833QX application information data sheet 59 rev. 1.1, 2012-03-08 4.2 connection of n.c. pins it is recommended to connect n.c. pins to gnd unless otherwise specified. since pins 10 and 46 are located next to high voltage pins (vs, mon5, ls1) these 2 n.c. pins can be also left unconnected in order to avoid huge current flow and damage of the system in case of short-circuit. 4.3 connection of adcgnd pin the adcgnd pin is chip-internal connected to reference ground. in order to provide full offset compensation and achieve full accuracy of adc1 the adcgnd pin must not be connected to board ground. adcgnd pin should be connected with a capacitor (100 nf) to varef only. 4.4 connection of exposed pad it is recommended to connect the exposed pad to gnd. 4.5 voltage regulators- blocking capacitors 4.6 additional external components table 11 external comp onent recommendation symbol function comment c vs blocking capacitor at vs pin > 20 f elco + 100 nf ceramic, esr < 1 ? c vddp blocking capacitor at vddp pin 1 f typ. + 100 nf ceramic, esr < 1 ? c vddext blocking capacitor at vddext pin 100 nf typ., esr < 1 ? c vddc blocking capacitor at vddc pin > 33 0 nf + 100 nf ceramic, esr < 1 ? c varef blocking capacitor at varef pin > 100 nf, esr < 1 ? table 12 external comp onent recommendation symbol function comment c hsx hf blocking capacitor at hsx pin 6.8 nf r monx resistor at monx pin 1 k ? r vbat_ resistor at vbat_sense pin 1 k ?
TLE9833QX application information data sheet 60 rev. 1.1, 2012-03-08 4.7 esd tests note: test for esd robustness to iec61000-4-2 ?gun test? (150pf, 330 ? ) will be performed. th e result and test condition can be provided in a test report table 13 esd ?gun test? performed test result unit remarks esd at pin lin, versus gnd > 6 kv 1) positive pulse 1) esd susceptibility ?esd gun? according lin emc 1.3 test s pecification, section 4.3 (iec 61000-4-2). tested by external test house (ibee zwickau). esd at pin lin, versus gnd < -6 kv 1) negative pulse
TLE9833QX electrical characteristics data sheet 61 rev. 1.1, 2012-03-08 5 electrical characteristics this chapter includes all rele vant electrical characterist ics of the product TLE9833QX. 5.1 general characteristics 5.1.1 absolute maximum ratings table 14 absolute maximum ratings 1) t j = -40 c to +150 c, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) parameter symbol values unit note / test condition number min. typ. max. voltages supply pins supply voltage vs v s -0.3 ? 40 v ? p_5.1.1 voltage vddp v ddp -0.3 ? 5.5 v ? p_5.1.2 voltage vddp v ddp -0.3 ? 6.0 v t < 100ms, in stop mode only p_5.1.50 output voltage vddext v ddext -0.3 ? 5.5 v ? p_5.1.3 voltage vddc v ddc -0.3 ? 1.6 v ? p_5.1.4 voltages high voltage pins battery voltage vbat_sense v bat_sense -27 ? 40 v ? p_5.1.5 output voltage hs v hs -0.3 ? 40 v ? p_5.1.6 input voltage at lin v lin -27 ? 40 v ? p_5.1.7 input voltage mon_x v mon_x_maxrate -40 ? 40 v ? p_5.1.8 input voltage ls v ls -0.3 ? 40 v ? p_5.1.9 voltages gpios voltage on any port pin v in -0.3 ? v ddp +0.3 v v in < 5.4v p_5.1.10 voltages others input voltage varef v aref -0.3 ? 5.3 v ? p_5.1.11 temperatures junction temperature t j -40 ? 150 c ? p_5.1.12 storage temperature t stg -55 ? 150 c ? p_5.1.13 esd resistivity esd resistivity hbm all pins v esd1 -2 ? 2 kv eia/jesd 22-a114b (1.5k ? , 100pf) p_5.1.14
TLE9833QX electrical characteristics data sheet 62 rev. 1.1, 2012-03-08 notes 1. stresses above the ones listed here may cause perma nent damage to the device. exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2. integrated protection func tions are designed to prevent ic destructi on under fault conditions described in the data sheet. fault conditions are considered as ?outside? normal operating range. pr otection functi ons are not designed for continuous repetitive operation. 5.1.2 functional range esd resistivity hbm pins hs, mon1, mon2, mon3, mon4, mon5, vs, vbatsense vs.gnd v esd2 -4 ? 4 kv eia/jesd 22-a114b (1.5k ? , 100pf) p_5.1.15 esd resistivity hbm pins lin vs. lingnd v esd2 -6 ? 6 kv eia/jesd 22-a114b (1.5k ? , 100pf) p_5.1.16 1) not subject to production test, specified by design. table 15 functional range t j = -40 c to +150 c, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) parameter symbol values unit note / test condition number min. typ. max. supply voltage in active mode v s_am 5.5 ? 27 v ? p_5.1.17 min. supply voltage in active mode with reduced functionality (microcontroller / flash with full operation) v s_ammin 3.0 ? 5.5 v 1) 1) reduced functionality (e.g. cranking pulse) - not part of production test p_5.1.18 supply voltage in v s_pd 3.0 ? 27 v ? p_5.1.19 supply voltage in sleep mode v s_sleep 3.0 ? 27 v ? p_5.1.20 supply voltage transients slew rate d v s /d t -1?1v/s 2) 2) not subject to production test, specified by design p_5.1.21 output sum current for all gpio pins i gpio,sum ? ? 60 ma ? p_5.1.22 operating frequency f sys 3) 3) specified function not guaranteed when limits are exceeded 5 ? 40 mhz ? p_5.1.23 junction temperature t j -40 ? 150 c ? p_5.1.24 table 14 absolute maximum ratings 1) t j = -40 c to +150 c, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) parameter symbol values unit note / test condition number min. typ. max.
TLE9833QX electrical characteristics data sheet 63 rev. 1.1, 2012-03-08 5.1.3 current consumption note: within the functional range the ic operates as de scribed in the circuit description. the electrical characteristics are specifi ed within the conditions given in the re lated electrical ch aracteristics table. 5.1.4 thermal resistance table 16 electrical characteristics 1) v s = 5.5v to 18v, t j = -40c to 85c, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) 1) not subject to production test, specified by design. parameter symbol values unit note / test condition number min. typ. max. current consumption @vs pin current consumption in active mode i active ? 30 40 ma fsys = 40 mhz no loads on pins, lin in recessive state, ls1, ls2, hs1 and hs2 off p_5.1.25 current consumption in stop mode i powerdown ? 85 95 a microcontroller in stop mode, lin recessive state, mon1-5 disabled, gpios open (no loads) p_5.1.26 current consumption in stop mode with cyclic sense enabled i powerdown2 ? ? 110 a microcontroller in stop mode, lin recessive state, gpios open (no loads) p_5.1.27 current consumption in sleep mode i sleep ? ? 25 a system in sleep mode, microcontroller not powered, lin recessive state, mon1-5 disabled and gpios open (no loads) p_5.1.28 table 17 thermal resistance parameter symbol values unit note / test condition number min. typ. max. junction to ambient r thja ? 23.9 ? k/w 1) 1) eia/jesd 52_2, fr4, 76.2 x 114.3 x 1.5 mm; 35 cu, 5 sn; 300 mm 2 p_5.1.29
TLE9833QX electrical characteristics data sheet 64 rev. 1.1, 2012-03-08 5.1.5 timing characteristics the transition times between the system modes are specified here. generally the timings are defined from the time when the corresponding bits in register pmcon0 are set until the sequence is terminated. table 18 system timing 1) v s = 5.5 v to 27 v, t j = -40 c to +150 c, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) 1) not subject to production test, specified by design. parameter symbol values unit note / test condition number min. typ. max. wake-up over battery t start ? ? 1 ms battery ramp-up till mcu reset is released; vs > 3v and reset = ?1? p_5.1.30 sleep mode exit t sleep - exit ? ? 1 ms rising/falling edge of any wake-up signal (lin, mons) till mcu reset is released; p_5.1.31 sleep mode entry t sleep - entry ? ? 330 s ? p_5.1.32 stop mode exit t stop - exit ? ? 300 s rising/falling edge of any wake-up signal (lin, mons, gpios) p_5.1.33 stop mode entry t stop - entry ? ? 300 s ? p_5.1.34
TLE9833QX electrical characteristics data sheet 65 rev. 1.1, 2012-03-08 5.2 power management unit (pmu) this chapter includes all electrical characteristics of the power management unit 5.2.1 pmu i/o supply parameters vddp table 19 electrical characteristics v s = 5.5 v to 27 v, t j = -40 c to +150 c, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) parameter symbol values unit no te / test condition number min. typ. max. specified outp ut current i vddp 0?60ma 1) 1) not subject to production test, specified by design p_5.2.1 required output capacitance c vddp 0.1 ? 10 f 1) esr < 1 ? p_5.2.2 output voltage including line regulation v ddpout 4.9 5.0 5.1 v i load < 90ma;vs > 5.5v p_5.2.3 output drop vs v ddpout ??+400mv i load < 70ma; 3v < v s < 5.5v p_5.2.4 dynamic load regulation v vddplor -50 ? 50 mv 1) 2 ... 70ma; c=470nf; di/dt=100ma/s p_5.2.5 dynamic line regulation v vddplir -25 ? 25 mv 1) v s = 5.5 ... 20v; dv/dt=5v/s p_5.2.6 power supply ripple rejection p ssrvddp 50 ? ? db 1) v s = 13.5v; f=0 ... 1khz; vr=2vpp p_5.2.7 over voltage detection v ddpov 5.05 ? 5.4 v v s > 5.5v; overvoltage leads to supply_nmi p_5.2.8 under voltage reset v ddpuv 2.4 ? 2.7 v v s > 5.5v p_5.2.9 over current shutdown i vddpoc 90 ? 180 ma ? p_5.2.10
TLE9833QX electrical characteristics data sheet 66 rev. 1.1, 2012-03-08 5.2.2 pmu core supply parameters vddc table 20 electrical characteristics v s = 5.5 v to 27 v, t j = -40 c to +150 c, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) parameter symbol values unit note / test condition number min. typ. max. specified outp ut current i vddc 0? 30ma 1) only used as internal core supply 1) vddc is not intended to be used as external voltage regulator p_5.2.11 required output capacitance c vddc 0.1 ? 10 f 2) esr < 1 ? 2) not subject to production test, specified by design p_5.2.12 output voltage including line regulation @ active mode v ddcout 1.44 1.5 1.56 v i load < 40ma p_5.2.13 output voltage including line regulation @ stop mode v ddcout 0.89 0.95 1.15 v i load < 200a p_5.2.14 dynamic load regulation v ddclor -50 ? 50 mv 2) 2 ... 30ma; c=330nf; di/dt=100ma/s p_5.2.15 dynamic line regulation v ddclir -25 ? 25 mv 2) v ddp = 2.5 ... 5.5v; dv/dt=5v/s p_5.2.16 over voltage detection v ddcov 1.61 ? 1.68 v overvoltage leads to supply_nmi p_5.2.17 under voltage reset v ddvuv 1.10 ? 1.19 v ? p_5.2.18 over current shutdown i vddcoc 35 ? 80 ma ? p_5.2.19
TLE9833QX electrical characteristics data sheet 67 rev. 1.1, 2012-03-08 5.2.3 vddext voltage regulator 5.0v table 21 electrical characteristics v s = 5.5 v to 27 v, t j = -40 c to +150 c, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) parameter symbol values unit note / test condition number min. typ. max. output current i vddext 0?20ma 1) p_5.2.20 output capacitance c vddext 10 ? 1000 nf 1) esr < 1 ? p_5.2.21 output voltage including line regulation v ddext 4.9 5.0 5.1 v i load < 20ma;vs > 5.5v p_5.2.22 output drop v s - v ddext ? +400 mv 1) i load < 20ma; 3v < v s < 5.5v p_5.2.23 dynamic load regulation v ddextlor -50 ? 50 mv 1) 2 ... 20ma; c=10nf; di/dt=10ma/s p_5.2.24 dynamic line regulation v vddextlir -25 ? 25 mv v s = 5.5 ... 20v; dv/dt=5v/s p_5.2.25 power supply ripple rejection 1) 1) not subject to production test, specified by design p ssrvddext 50 ? ? db v s = 13.5v; f=0 ... 1khz; v r =2vpp p_5.2.26 over voltage detection v vddextov 5.05 ? 5.4 v v s > 5.5v p_5.2.27 under voltage detection v vddextuv 2.6 ? 2.9 v 2) v s > 3.0v 2) when the condition is met, the bit vddext_ctrl.vddext_short will be set p_5.2.28 over current diagnostic i vddextoc 25 ? 70 ma ? p_5.2.29
TLE9833QX electrical characteristics data sheet 68 rev. 1.1, 2012-03-08 5.3 system clocks 5.3.1 oscillators and pll table 22 electrical characteristics v s = 5.5 v to 27 v, t j = -40 c to +150 c, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) parameter symbol values unit note / test condition number min. typ. max. pmu oscillators (power management unit) frequency of lp_clk f lp_clk1 14 18 22 mhz this clock is used at startup and can be used in case the pll fails p_5.3.1 frequency of lp_clk2 f lp_clk2 70 100 130 khz this clock is used for cyclic wake and cyclic sense p_5.3.2 cgu oscillator (clock genera tion unit microcontroller) short term frequency deviation f trimst -1.5% 5 +1.5% mhz 1) with respect to nominal configured system frequency within one lin message (< 10ms ... 100ms) p_5.3.3 long term frequency deviation f trimlt -3.0% 5 +3.0% mhz with respect to nominal configured system frequency over lifetime and temperature p_5.3.4 cgu-osc start-up time t osc ? ? 10 s startup time osc from sleep mode and stop mode, power supply stable p_5.3.5 pll (clock generation unit microcontroller) vco frequency range mode 0 f vco-0 48 ? 112 mhz vcosel =?0? p_5.3.6 vco frequency range mode 1 f vco-1 96 ? 160 mhz vcosel =?1? p_5.3.7 input frequency range f osc 4 ? 16 mhz ? p_5.3.8 xtal1 input freq. range f osc 4 ? 16 mhz ? p_5.3.9 output freq. range f pll 0.04687 ? 80 mhz ? p_5.3.10 free-running frequency mode 0 f vcofree_0 ? ? 38 mhz vcosel =?0? p_5.3.11 free-running frequency mode 1 f vcofree_1 ? ? 76 mhz vcosel =?1? p_5.3.12 input clock high/low time t high/low 10 ? ? ns ? p_5.3.13 peak period jitter t jp -500 ? 500 ps for k=1 p_5.3.14
TLE9833QX electrical characteristics data sheet 69 rev. 1.1, 2012-03-08 5.3.2 external clock para meters xtal1, xtal2 accumulated jitter jacc ? ? 5 ns for k=1 p_5.3.15 lock-in time t l ? ? 200 s ? p_5.3.16 1) v ddc = 1.5 v, t j = 25 c table 23 functional range v s = 5.5 v to 27 v, t j = -40 c to +150 c, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) parameter symbol values unit note / test condition number min. typ. max. input voltage range limits for signal on xtal1 v ix1_sr -1.7 + v ddc ?1.7 v 1) 1) overload conditions must not occur on pin xtal1. p_5.3.17 input voltage (amplitude) on xtal1 v ax1_sr 0.3 x v ddp ?? v 2) peak-to-peak voltage 2) the amplitude voltage v ax1 refers to the offset voltage v off . this offset voltage must be stable during the operation and the resulting voltage peaks must remain within the limits defined by v ix1 . p_5.3.18 xtal1 input current i il ??20a0 v < v in < v ddc p_5.3.19 oscillator frequency f osc 4 ? 24 mhz clock signal p_5.3.20 oscillator frequency f osc 4 ? 16 mhz crystal or resonator p_5.3.21 high time t 1 6 ? ? ns ? p_5.3.22 low time t 2 6 ? ? ns ? p_5.3.23 rise time t 3 ? 8 8 ns ? p_5.3.24 fall time t 4 ? 8 8 ns ? p_5.3.25 table 22 electrical characteristics v s = 5.5 v to 27 v, t j = -40 c to +150 c, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) parameter symbol values unit note / test condition number min. typ. max.
TLE9833QX electrical characteristics data sheet 70 rev. 1.1, 2012-03-08 5.4 flash parameters this chapter includes the parameters for the 48 kbyte embedded flash module. table 24 flash characteristics 1) v s = 5.5 v to 27 v, t j = -40 c to +150 c, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) 1) not subject for production test, specified by design parameter symbol values unit note / test condition number min. typ. max. programming time per 128 byte page t pr ? 2) 3 2) programming and erase times depend on the internal flash clock source. the control state machine needs a few system clock cycles. this requirement is only rele vant for extremely low system frequencies. 3.5 ms ? p_5.4.1 erase time per sector/page t er ? 2) 4 4.5 ms ? p_5.4.2 data retention time t ret 20 ? ? years 1,000 erase / program cycles p_5.4.3 flash erase endurance for user sectors n er 30 ? ? kcycles data retention time 5 years p_5.4.4
TLE9833QX electrical characteristics data sheet 71 rev. 1.1, 2012-03-08 5.5 parallel ports (gpio) 5.5.1 functional range 5.5.2 dc parameters these parameters apply to the io voltage range, 4.5 v v ddp 5.5 v. note: operating conditions apply. keeping signal levels within the limits specified in th is table ensures operation without overload conditions. for signal levels outside these specifications, also refer to the specification of the overload current i ov . table 25 functional range v s = 5.5 v to 27 v, t j = -40 c to +150 c, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) parameter symbol values unit note / test condition number min. typ. max. output current on any pin i oh , i ol ??20ma 1) 2) 1) one of these limits must be kept. 2) not subject to production test, specified by design p_5.5.1 max output current for all gpios i max ??60ma 1) 2) p_5.5.2 table 26 dc characteristics v s = 5.5 v to 27 v, t j = -40 c to +150 c, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) parameter symbol values unit note / test condition number min. typ. max. input low voltage (all except xtal1) v il -0.3 ? 0.3 x v ddp v ? p_5.5.3 input high voltage (all except xtal1) v ih 0.7 x v ddp ? v ddp + 0.3 v ? p_5.5.4 input hysteresis 1) hys 0.11 x v ddp ? ? v series resistance = 0 ? p_5.5.5 output low voltage v ol ??1.0v 2) i ol i olmax p_5.5.6 output low voltage v ol ??0.4v 2) i ol 3) i olnom p_5.5.7 output high voltage 4) v oh v ddp - 1.0 ? ? v 2) i oh i ohmax p_5.5.8 output high voltage v oh v ddp - 0.4 ? ? v 2)3) i oh i ohnom p_5.5.9 input leakage current (port 2) i oz1 -400 ? +400 na t j 85c, 0 v < v in < v ddp p_5.5.10 input leakage current (all other) 5) i oz2 -5 ? +5 a t j 85c, 0.45 v < v in < v ddp p_5.5.11
TLE9833QX electrical characteristics data sheet 72 rev. 1.1, 2012-03-08 input leakage current (all other) i oz2 -15 ? +15 a t j 150c, 0.45 v < v in < v ddp p_5.5.12 pull level keep current i plk -240 ? +240 a 6) v pin v ih (up) v pin v il (dn) p_5.5.13 pull level force current i plf -1.5 ? +1.5 ma 6) v pin v il (up) v pin v ih (dn) p_5.5.14 pin capacitance (digital inputs/outputs) c io ? ? 10 pf ? p_5.5.15 1) not subject to production test, specified by design. 2) the maximum deliverable output current of a port driver dep ends on the selected output dr iver mode. the limit for pin groups must be respected. 3) as a rule, with decreasing output current the output levels approac h the respective supply level ( v ol gnd , v oh v ddp ). however, only the levels for nominal output currents are verified. 4) this specification is not valid for out puts which are switched to open drain mode. in this case the respective output will fl oat and the voltage is determined by the external circuit. 5) the given values are worst-case values. in production test, th is leakage current is only te sted at 125c; other values are ensured by correlation. for derating, please refer to the following descriptions: leakage derating depending on temperature ( t j = junction temperature [c]): i oz = 0.05 e (1.5 + 0.028tj) [ a]. for example, at a temperature of 95 c the resulting leakage current is 3.2 a. leakage derating depending on voltage level ( ? v = v ddp - v pin [v]): i oz = i oztempmax - (1.6 ? v) [ a] this voltage derating formula is an approxim ation which applies for maximum temperature. 6) keep current: limit the current through this pin to the indi cated value so that the enabled pull device can keep the default pin level: v pin v ih for a pull-up; v pin v il for a pull-down. force current: drive the indicat ed minimum current through this pin to change the default pin level driven by the enabled pull device: v pin v il for a pull-up; v pin v ih for a pull-down. these values apply to the fixed pull-devices in dedicated pins and to the user-selectable pull-devices in general purpose io pins. table 26 dc characteristics v s = 5.5 v to 27 v, t j = -40 c to +150 c, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) parameter symbol values unit note / test condition number min. typ. max.
TLE9833QX electrical characteristics data sheet 73 rev. 1.1, 2012-03-08 note: stresses above the values listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only. functional operation of the device at these or any other conditions above those indicated in the operational sect ions of this specification is not im plied. exposure to absolute maximum rating conditions for an extended time may affect device reliability. during absolute maximum rati ng overload conditions ( v in > v ddp or v in < gnd ) the voltage on v ddp pins with respect to ground ( gnd ) must not exceed the values defined by the absolute maximum ratings. table 27 current limits fo r port output drivers 1) 1) not subject to production test, specified by design. port output driver mode maximum output current ( i olmax , - i ohmax ) nominal output current ( i olnom , - i ohnom ) number vddp 4.5v vddp < 4.5v vddp 4.5v vddp < 4.5v strong driver 7.5 ma 7.5 ma 2.5 ma 2.5 ma p_5.5.16 medium driver 4 ma 2.5 ma 1.0 ma 1.0 ma p_5.5.17 weak driver 0.5 ma 0.5 ma 0.1 ma 0.1 ma p_5.5.18
TLE9833QX electrical characteristics data sheet 74 rev. 1.1, 2012-03-08 5.6 lin transceiver 5.6.1 electrical characteristics table 28 electrical characteristics lin transceiver v s = 5.5v - 18v, t j = -40 c to +150 c, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) parameter symbol values unit note / test condition number min. typ. max. bus receiver interface receiver threshold voltage, recessive to dominant edge v th_dom 0.4 v s 0.45 v s 0.53 x v s v sae j2602 p_5.6.1 receiver dominant state v busdom -27 ? 0.4 v s v lin spec 2.1 (par. 17) p_5.6.2 receiver threshold voltage, dominant to recessive edge v th_rec 0.47 x v s 0.55 v s 0.6 v s v sae j2602 p_5.6.3 receiver recessive state v busrec 0.6 v s ? 1.15 v s v 1) lin spec 2.1 (par. 18) p_5.6.4 receiver center voltage v bus_cn t 0.475 v s 0.5 v s 0.525 v s v 2) lin spec 2.1 (par. 19) p_5.6.5 receiver hysteresis v hys 0.07 v s 0.12 v s 0.175 v s v 3) lin spec 2.1 (par. 20) p_5.6.6 wake-up threshold voltage v bus,wk 0.4 v s 0.5 v s 0.6 v s v ? p_5.6.7 dominant time for bus wake- up t wk,bus 3 ? 15 s to achieve the required wake-up time from 30 s to 150 s according to lin spec., an additional digital filter is added (see pmu chapter) p_5.6.8 bus transmitter interface bus recessive output voltage v bus,ro 0.8 v s ? v s v v txd = high level p_5.6.9 bus short circuit current i bus,sc 40 100 150 ma v bus = 13.5 v p_5.6.10 leakage current i bus_no_ gnd -1000 -70 ? a v s = 0 v; v bus = -12 v; lin spec 2.1 (par. 15) p_5.6.11 leakage current i bus_no_ bat ?1020 a v s = 0 v; v bus = 18 v; lin spec 2.1 (par. 16) p_5.6.12 leakage current i bus_pas _dom -1 ? ? ma v s = 18 v; v bus = 0 v; lin spec 2.1 (par. 13) p_5.6.13 leakage current i bus_pas _rec ?? 20 a v s = 8 v; v bus = 18 v; lin spec 2.1 (par. 14) p_5.6.14 bus pull-up resistance r bus 20 30 47 k ? normal mode lin spec 2.1 (param. 26) p_5.6.15 lin input capacity c lin_in ?1530 pf 4) p_5.6.80
TLE9833QX electrical characteristics data sheet 75 rev. 1.1, 2012-03-08 ac characteristics - transceiver normal slope mode propagation delay bus dominant to rxd low t d(l),r 0.1 1 6 s (lin spec 2.1; param. 31) p_5.6.16 propagation delay bus recessive to rxd high t d(h),r 0.1 1 6 s (lin spec 2.1; param. 31) p_5.6.17 receiver delay symmetry t sym,r -2 ? 2 s t sym,r = t d(l),r - t d(h),r ;(lin spec 2.1; param. 31) p_5.6.18 duty cycle d1 normal slope mode (for worst case at 20 kbit/s) t duty1 0.396 ? ? 5) duty cycle 1 th rec (max) = 0.744 v s ; th dom (max) = 0.581 v s ; v s = 5.5 ? 18 v; t bit = 50 s; d1 = t bus_rec(min) /2 t bit ; lin spec 2.1 (par. 27) p_5.6.19 duty cycle d2 normal slope mode (for worst case at 20 kbit/s) t duty2 ? ? 0.581 6) duty cycle 2 th rec (max) = 0.422 v s ; th dom (max) = 0.284 v s ; v s = 5.5 ? 18 v; t bit = 50 s; d2 = t bus_rec(max) /2 t bit ; lin spec 2.1 (par. 28) p_5.6.20 ac characteristics - transceiver low slope mode propagation delay bus dominant to rxd low t d(l),r 0.1 1 6 s (lin spec 2.1; param. 31) p_5.6.21 propagation delay bus recessive to rxd high t d(h),r 0.1 1 6 s (lin spec 2.1; param. 31) p_5.6.22 receiver delay symmetry t sym,r -2 ? 2 s t sym,r = t d(l),r - t d(h),r ; (lin spec 2.1; param. 32) p_5.6.23 table 28 electrical characteristics (cont?d) lin transceiver v s = 5.5v - 18v, t j = -40 c to +150 c, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) parameter symbol values unit note / test condition number min. typ. max.
TLE9833QX electrical characteristics data sheet 76 rev. 1.1, 2012-03-08 duty cycle d3 (for worst case at 10,4 kbit/s) t duty1 0.417 ? ? 7) duty cycle 3 th rec (max) = 0.778 v s ; th dom (max) = 0.616 v s ; v s = 5.5 ? 18 v; t bit = 96 s; d3 = t bus_rec(min) /2 t bit ; lin spec 2.1 (par. 29) p_5.6.24 duty cycle d4 (for worst case at 10,4 kbit/s) t duty2 ? ? 0.590 duty cycle 4 th rec (max) = 0.389 v s ; th dom (max) = 0.251 v s ; v s = 5.5 ? 18 v; t bit = 96 s; d4 = t bus_rec(max) /2 t bit ; lin spec 2.1 (par. 30) p_5.6.25 ac characteristics - transceiver fast slope mode propagation delay bus dominant to rxd low t d(l),r 0.1 1 6 s ? p_5.6.26 propagation delay bus recessive to rxd high t d(h),r 0.1 1 6 s ? p_5.6.27 receiver delay symmetry t sym,r -1 ? 1 s t sym,r = t d(l),r - t d(h),r ; p_5.6.28 duty cycle d5 (for worst case at 40 kbit/s) t duty1 0.395 ? ? 6) duty cycle 5 th rec (max) = 0.744 v s ; th dom (max) = 0.581 v s ; v s = 5.5 ? 18 v; t bit = 25s; d1 = t bus_rec(min) /2 t bit ; p_5.6.29 duty cycle d6 (for worst case at 40 kbit/s) t duty2 ? ? 0.581 6) duty cycle 6 th rec (max)= 0.422 v s ; th dom (max)= 0.284 v s ; v s = 5.5 ? 18 v; t bit = 25 s; d2 = t bus_rec(max) /2 t bit ; lin spec 2.1 (par. 28) p_5.6.30 ac characteristics - flash mode propagation delay bus dominant to rxd low t d(l),r 0.1 0.5 6 s ? p_5.6.31 table 28 electrical characteristics (cont?d) lin transceiver v s = 5.5v - 18v, t j = -40 c to +150 c, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) parameter symbol values unit note / test condition number min. typ. max.
TLE9833QX electrical characteristics data sheet 77 rev. 1.1, 2012-03-08 propagation delay bus recessive to rxd high t d(h),r 0.1 0.5 6 s ? p_5.6.32 receiver delay symmetry t sym,r -1.0 ? 1.0 s t sym,r = t d(l),r - t d(h),r ; p_5.6.33 duty cycle d7 (for worst case at 115 kbit/s) for +1 s receiver delay symmetry t duty1 0.399 ? ? 8) duty cycle d7 th rec (max) = 0.744 v s ; th dom (max) = 0.581 v s ; v s = 13.5 v; t bit = 8.7 s; d7 = t bus_rec(min) /2 t bit ; p_5.6.34 duty cycle d8 (for worst case at 115 kbit/s) for +1 s receiver delay symmetry t duty2 ? ? 0.578 6) duty cycle 8 th rec (max) = 0.422 v s ; th dom (max) = 0.284 v s ; v s = 13.5 v; t bit = 8.7 s; d8 = t bus_rec(max) /2 t bit ; p_5.6.35 txd dominant time out t timeout 61220 ms 8) v txd = 0 v p_5.6.36 1) maximum limit specified by design. 2) v bus_cnt = ( v th_dom + v th rec )/2 3) v hys = v busrec - v busdom 4) this parameter is not subject to production test 5) bus load concerning lin spec 2.1: load 1 = 1 nf / 1 k ? = c bus / r bus load 2 = 6.8 nf / 660 ? = c bus / r bus load 3 = 10 nf / 500 ? = c bus / r bus 6) bus loads: load 1 = 1 nf / 1 k ? = c bus / r bus 7) bus load concerning lin spec 2.1: load 1 = 1 nf / 1 k ? = c bus / r bus load 2 = 6.8 nf / 660 ? = c bus / r bus load 3 = 10 nf / 500 ? = c bus / r bus 8) timeout can be disabled optional table 28 electrical characteristics (cont?d) lin transceiver v s = 5.5v - 18v, t j = -40 c to +150 c, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) parameter symbol values unit note / test condition number min. typ. max.
TLE9833QX electrical characteristics data sheet 78 rev. 1.1, 2012-03-08 5.7 high-speed synchr onous serial interface the table below provides the ssc timing in the TLE9833QX. figure 32 ssc master mode timing table 29 ssc master mode timing (operating conditions apply; cl = 50 pf) v s = 5.5 v to 27 v, t j = -40 c to +150 c, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) parameter symbol values unit note / test condition number min. typ. max. sclk clock period t 0 1) 2 * t ssc 1) t sscmin = t cpu = 1/ f cpu . when f cpu = 24 mhz, t 0 = 83.3 ns. t cpu is the cpu clock period. ? ? ? p_5.7.1 mtsr delay from sclk t 1 10 ? ? ns ? p_5.7.2 mrst setup to sclk t 2 10 ? ? ns ? p_5.7.3 mrst hold from sclk t 3 15 ? ? ns ? p_5.7.4 ssc_tmg1 sclk 1) mtsr 1) t 1 t 1 mrst 1) t 3 data valid t 2 t 1 1) this timing is based on the following setup: con.ph = con.po = 0. t 0
TLE9833QX electrical characteristics data sheet 79 rev. 1.1, 2012-03-08 5.8 measurement unit 5.8.1 analog digital converter 8-bit 5.8.2 measurement unit (vbat_se nse - supply voltage attenuator) table 30 dc specifications adc 8 bit v s = 5.5 v to 27 v, t j = -40 c to +150 c, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) parameter symbol values unit note / test condition number min. typ. max. resolution ? ? 8 ? bit ? p_5.8.1 offset error ? -10 4 +10 mv ? p_5.8.2 gain single-ended i nput mode gse ? 1 ? ? p_5.8.3 input voltage single-ended mode v ainp , v ainn 0? v dd1v5_a v ? p_5.8.4 gain differential input mode gdf 1.24 ? ? ? p_5.8.5 common input voltage in differential mode v icm 0.5 0.6 v ddp /2 +0.1 ?v icm =(v ainp + v ainn )/2 p_5.8.6 gain error ? -5 1.5 +5 %fsr ? p_5.8.7 differential nonlinearity (d nl) ? -1.5 0.5 +1.5 lsb ? p_5.8.8 integral nonlinearity (inl) ? -3 1.5 3 lsb ? p_5.8.9 table 31 supply voltag e signal conditioning v s = 5.5 v to 27 v, t j = -40 c to +150 c, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) parameter symbol values unit note / test condition number min. typ. max. battery voltage measurement v bat_sense nominal operating input voltage range 1) v s/bat_sense 3 ? 20 v max. value corresponds to typ. adc full scale input p_5.8.10 measurement input resistance r in,vs/vbat_sens e 200 289 380 k ? pd_n=1 (on-state) p_5.8.11 measurement input leakage current i leak 0 ? 1.0 a pd_n=0 (off-state), v bat_sense =13.5v p_5.8.12 overall (calibrated) measurement accuracy after a/d-conversion 2) v bat_sense / v s 8-bit adc ? v batadc8b -250 ? 250 mv v s = 5.5v to 18v, t j = 40..85c p_5.8.13 v bat_sense / v s 10-bit adc ? v batadc10b -200 ? 200 mv v s = 5.5v to 18v, t j = 40..85c p_5.8.14
TLE9833QX electrical characteristics data sheet 80 rev. 1.1, 2012-03-08 5.8.3 measurement functions monito ring input voltage attenuator v dd5_sense ? v ddp_sense -150 ? 150 mv ? p_5.8.15 v dd1v5_sense ? v ddc_sense -45 ? 45 mv ? p_5.8.16 1) this parameter is not subject to production test 2) the device is calibrated based on an external 1k ? resistor table 32 monitoring input voltage attenuation v s = 5.5 v to 27 v, t j = -40 c to +150 c, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) parameter symbol values unit note / test condition number min. typ. max. power supply input resistance 1) 1) not subject to production test, specified by design. r in 300 400 500 k ? pd_n=1 (on-state) v mon_x =0 to 18v if vmon_sen_sel_inrange = 0 p_5.8.17 input resistance r in 250 ? ? k ? v mon_x =0 to 28v if vmon_sen_sel_inrange = 1 >200 k ? under all other conditions p_5.8.18 timing characteristics analog multiplexer settling time t muxsettle ? ? 30 s this time frame is valid from writing the corresponding selection register to proper settling of the voltage at channel 7 of the 10-bit adc p_5.8.19 overall (calibrated) measurement accuracy after a/d-conversion v monx 10-bit adc ? v monxad c10b -200 ? 200 mv v s =5.5v to 18v, t j = 40..85c p_5.8.20 table 31 supply voltag e signal conditioning v s = 5.5 v to 27 v, t j = -40 c to +150 c, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) parameter symbol values unit note / test condition number min. typ. max.
TLE9833QX electrical characteristics data sheet 81 rev. 1.1, 2012-03-08 5.8.4 temperature sensor module table 33 electrical characteristics temperature sensor module v s = 5.5 v to 27 v, t j = -40 c to +150 c; all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) parameter symbol values unit note / test condition number min. typ. max. linear temperature range t range -40 175 c ? p_5.8.21 output voltage v temp at t 0 =273 k (0c) mode 1 a ? 0.4893 ? v 1) dvbe_mode=0 t=273k (0c) 1) not subject to production test, specified by design p_5.8.22 output voltage v temp at t 0 =273 k (0c) mode 2 a ? 0.5365 ? v dvbe_mode=1 t 0 =273 k (0c) p_5.8.23 temperature sensitivity b in mode 1 b ? 1.685 ? mv/k 1) dvbe_mode=0 p_5.8.24 temperature sensitivity b mode 2 b ? 1.834 ? mv/k dvbe_mode=1 p_5.8.25 accuracy_1 2) 2) accuracy with reference to on-chip temperature calibration measurement acc_1 -10 ? 10 c -40c < t j < 125c p_5.8.26 accuracy_2 acc_2 -15 ? 15 c 125c < t j < 175c p_5.8.27
TLE9833QX electrical characteristics data sheet 82 rev. 1.1, 2012-03-08 5.9 adc - 10-bit 5.9.1 varef 5.9.1.1 functional range 5.9.1.2 electrical characteristics table 34 functional range v s = 5.5 v to 27 v, t j = -40 c to +150 c, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) parameter symbol values unit note / test condition number min. typ. max. varef input voltage v aref_in 0? v ddp +0.3 v ? p_5.9.1 table 35 10-bit adc - varef v s = 5.5 v to 27 v, t j = -40 c to +150 c, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) parameter symbol values unit note / test condition number min. typ. max. output capacitance c varef 0.1 ? 1 f esr < 1 ? p_5.9.2 reference output voltage v aref 4.95 5 5.05 v v s > 5.5v p_5.9.3 dc supply voltage rejection dc psrvaref 30 ? ? db 1) 1) not subject to production test, specified by design. p_5.9.4 supply voltage ripple rejection ac psrvaref 26 ? ? db 1) v s = 13.5v; f=0 ... 1khz; vr=2vpp p_5.9.5 turn on time t so ??200s 1) cext=100nf pd_n to 99.9% of final value (test setup: measure 1 , calculate 5 . p_5.9.6
TLE9833QX electrical characteristics data sheet 83 rev. 1.1, 2012-03-08 5.9.2 analog/digital converter parameters these parameters describe the conditions for optimum adc performance. note: operating conditions apply. table 36 a/d converter characteristics v s = 5.5 v to 27 v, t j = -40 c to +150 c; all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) parameter symbol values unit note / test condition number min. typ. max. analog reference supply v arefsr v agnd + 1.0 ? v ddpa + 0.05 v 1) p_5.9.7 analog reference ground v agndsr gnd - 0.05 ?1.5v 2) p_5.9.8 analog input voltage range v ain v agnd ? v aref v 3) p_5.9.9 analog clock frequency f adci 0.5 ? 20 mhz 4) p_5.9.10 conversion time for 10-bit result 5) t c10 (13 + stc) t adci + 2 x t sys (13 + stc) t adci + 2 x t sys (13 + stc) t adci + 2 x t sys ? ? p_5.9.11 conversion time for 8-bit result t c8 (11 + stc) t adci + 2 t sys (11 + stc) t adci + 2 t sys (11 + stc) t adci + 2 t sys ? ? p_5.9.12 wake-up time from analog stop mode, fast mode t waf ??4s 6) p_5.9.13 wake-up time from analog stop mode, slow mode t was ??15s 6) p_5.9.14 total unadjusted error 7) tue -15 ? + 15 lsb 1) v aref = 5.0 v1% p_5.9.15 dnl error ea dnl ea -2 ? + 2 lsb ? p_5.9.16 inl error ea inl ea -5 ? + 5 lsb ? p_5.9.17 gain error ea gain ea -10 ? + 10 lsb ? p_5.9.18 offset error ea off ea -2 ? + 2 lsb ? p_5.9.19 total capacitance of an analog input c aint ??10pf 6)8) p_5.9.20 switched capacitance of an analog input c ains ??4pf 6)8) p_5.9.21 resistance of the analog input path r ain ??2k ? 6)8) p_5.9.22 total capacitance of the reference input c areft ??15pf 6)8) p_5.9.23 switched capacitance of the reference input c arefs ??7pf 6)8) p_5.9.24 resistance of the reference input path r aref ??2k ? 6)8) p_5.9.25
TLE9833QX electrical characteristics data sheet 84 rev. 1.1, 2012-03-08 1)tue is tested at v aref = 5v 1%, v agnd = 0 v. it is verified by design for all other voltages within the defined voltage range. the specified tue is valid only if v aref and v agnd remain stable during the measurement time. 2) only valid in case of external supplied reference voltage. 3) v ain may exceed v agnd or v arefx up to the absolute maximum ratings. however, the conversion result in these cases will be 000 h or 3ff h , respectively. 4) the limit values for f adci must not be exceeded when selecting the peripheral frequency and the prescaler setting. 5) this parameter includes the sample time (also the additional sample time specif ied by stc), the time to determine the digital result and the time to load the result register with the conversion result. 6) not subject to production test, specified by design. 7) the total unadjusted error tue is the maximum deviation from th e ideal adc transfer curve, not the sum of individual errors. all error specifications are based on meas urement methods standar dized by ieee 1241.2000. 8) these parameter values cover the complete operating ran ge. under relaxed operating conditions (temperature, supply voltage) typical values can be used for calculation. at room temperature and nominal supply voltage the following typical values can be used: c ainttyp = 12 pf, c ainstyp = 5 pf, r aintyp = 1.0 k ? , c arefttyp = 15 pf, c arefstyp = 10 pf, r areftyp = 1.0 k ? .
TLE9833QX electrical characteristics data sheet 85 rev. 1.1, 2012-03-08 5.10 high-voltag e monitor input the parameters of the analog measurement ar e listed in the chapter measurement interface. table 37 electrical characteristics v s = 5.5 v to 27 v, t j = -40 c to +150 c, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) parameter symbol values unit note / test condition number min. typ. max. input pin characteristics wake-up/monitoring threshold voltage v month 0.4*v s 0.5*v s 0.6*v s v without external serial resistor r s (with r s : ? v = i pd/pu * r s ); p_5.10.1 threshold hysteresis v month,hys 0.02*v s 0.06*v s 0.12*v s v in all modes; without external serial resistor r s (with r s : ? v = i pd/pu * r s ); p_5.10.2 pull-up current monx_ctrl_sts.monx_pu = high monx_ctrl_sts.monx_pd = low i pu, monx -20 -10 -1 a 0 v < v mon_in < v s - 2 v p_5.10.3 pull-up current monx_ctrl_sts.monx_pu = high monx_ctrl_sts.monx_pd = high i pu, monx -20 -10 -1 a 0.6*v s < v mon_in < v s - 2 v p_5.10.4 pull-down current monx_ctrl_sts.monx_pu = low monx_ctrl_sts.monx_pd = high i pd, monx 41018a2 v < v mon_in < v s p_5.10.5 pull-down current monx_ctrl_sts.monx_pu = high monx_ctrl_sts.monx_pd = high i pd, monx 41018a2 v < v mon_in < 0.4*v s p_5.10.6 input leakage current monx_ctrl_sts.monx_pu = low monx_ctrl_sts.monx_pd = low i lk,i -2 ? 2 a 0 v < v mon_in < 28 v p_5.10.7
TLE9833QX electrical characteristics data sheet 86 rev. 1.1, 2012-03-08 5.11 high side switches 5.11.1 functional range 5.11.2 electrical characteristics table 38 functional range t j = -40 c to +150 c, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) parameter symbol values unit note / test condition number min. typ. max. nominal operating voltage v s 5.5 ? 27 v ? p_5.11.1 current range for sleep mode / stop mode i hs max sleep_pd ? ? 40 ma cyclic sense mode p_5.11.2 pwm frequency of hs with slew rate control f pwm_w_sr 0? 10khz 1) frequency must be configured in the pwm generator 1) not subject to production test, specified by design. p_5.11.3 pwm frequency of hs without slew rate control f pwm_w/o_sr 0? 25 2) 2) referring to a 47ohm series resistor to charge an external power mos gate khz 1) frequency must be configured in the pwm generator p_5.11.4 table 39 electrical characteristics v s = 5.5 v to 27 v, t j = -40 c to +150 c, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) parameter symbol values unit note / test condition number min. typ. max. maximum ratings output voltage v hsxout -0.3 ? v s v min. value referred to gnd_a p_5.11.5 output hs on-state resistance r on ??20 ? v s =5.5 to 27 v, ids=100ma, higher resistance below v s =5.5v p_5.11.6 output leakage current i leakage ? ? 2 a output off 0 v < v xlo < v s ; t j < 85 c p_5.11.7 output slew rate (rising) with slew rate control sr raise_w_sr 1 ? 10 v/s 10% to 90% of v s v s = 9 to 18v r l =300 ? 1) p_5.11.8
TLE9833QX electrical characteristics data sheet 87 rev. 1.1, 2012-03-08 output slew rate (falling) with slew rate control sr fall_w_sr -10 ? -1 v/s 90% to 10% of v s v s = 9 to 18v r l =300 ? 1) p_5.11.9 output slew rate (rising) without slew rate control sr raise_w/o_sr 25 ? 60 v/s 10% to 90% of v s v s = 9 to 18v r l =300 ? 1) p_5.11.10 output slew rate (falling) without slew rate control sr fall_w/o_sr ?30 ? -10 v/s 90% to 10% of v s v s = 9 to 18v r l =300 ? 1) p_5.11.11 turn on delay time t in-hs ? ? 3 s on = 1 to 10% of v s r l =300 ? p_5.11.12 turn on time t on 1 ?15s v s =13.5v hs_on=1 to 90% of v s r l =300 ? t j =25c p_5.11.13 turn off time t off 1 ?15s v s =13.5v hs_on= 0 to 10% of v s r l =300 ? ; t j =25c p_5.11.14 load current limitation i short -1.2 ? ? a 1) vs =27v, vhs=0v, max duration 200 s p_5.11.15 over-current detection overcurrent threshold 0 i octh0 4?18ma 1) hsx_oc_sel =00 p_5.11.16 overcurrent threshold 0 hysteresis i octh0,hyst 2?5ma 1) hsx_oc_sel =00 p_5.11.17 overcurrent threshold 1 i octh1 50 ? 75 ma hsx_oc_sel =01 p_5.11.18 overcurrent threshold 1 hysteresis i octh1,hyst 5?15ma 1) hsx_oc_sel =01 p_5.11.19 overcurrent threshold 2 i octh2 100 ? 150 ma hsx_oc_sel =10 p_5.11.20 overcurrent threshold 2 hysteresis i octh2,hyst 10 ? 30 ma 1) hsx_oc_sel =10 p_5.11.21 overcurrent threshold 3 i octh3 150 ? 220 ma hsx_oc_sel =11 p_5.11.22 overcurrent threshold 3 hysteresis i octh3,hyst 20 ? 50 ma 1) hsx_oc_sel =11 p_5.11.23 overall over-current filter time t ocft 8?80s 1) vs =13.5v, r l =100 ? , hs_on to oc_sd (including switch- on time) p_5.11.24 on-state open load detection open load threshold i olonth 4?18ma 1) ol_en = 1; hs_on = 1 p_5.11.25 table 39 electrical characteristics (cont?d) v s = 5.5 v to 27 v, t j = -40 c to +150 c, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) parameter symbol values unit note / test condition number min. typ. max.
TLE9833QX electrical characteristics data sheet 88 rev. 1.1, 2012-03-08 hysteresis i olonhys 1?4ma 1) ol_en = 1; hs_on = 1 p_5.11.26 off-state open load detection open load voltage threshold v olth1 0.5* v s 0.67 * v s 0.85* v s v i ol_test ; open load activated; olth_sel = 1 p_5.11.27 hysteresis v olhys 0.1* v s ?0.3* v s v iol_sel = 1 p_5.11.28 open load output current i ol_test -150 ? -25 a iol_sel = 0 p_5.11.29 open load output current i ol_test -1.5 ? -0.5 ma iol_sel = 1 p_5.11.30 cyclic sense mode on-state resistance r on,static ??40 ? definition: differential resistance or resistance at 40 ma p_5.11.31 output slew rate (rising) sr rise 1) 1 ? ? v/s 10% to 90% of v s v s = 9 to 18v r l =300 ? 1) p_5.11.32 output slew rate (falling) sr fall 1) ? ? -1 v/s 90% to 10% of v s v s = 9 to 18v r l =300 ? p_5.11.33 delay time cyclic_on-hs t in-cyc ? ? 2 s on =1 to 10% of v s rl=300 ? p_5.11.34 turn-on time t on ??15s v s =13.5v on=1 to 90% r l =300 ? p_5.11.35 turn-off time t off ??15s v s =13.5v on=0 to 10% of v s r l =300 ? ; t j =25c p_5.11.36 1) not subject to production test, specified by design. table 39 electrical characteristics (cont?d) v s = 5.5 v to 27 v, t j = -40 c to +150 c, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) parameter symbol values unit note / test condition number min. typ. max.
TLE9833QX electrical characteristics data sheet 89 rev. 1.1, 2012-03-08 5.12 low side switches 5.12.1 functional range note: within the functional range the ic operates as de scribed in the circuit description. the electrical characteristics are specifi ed within the conditions given in the re lated electrical ch aracteristics table. 5.12.2 electrical characteristics table 40 functional range t j = -40 c to +150 c, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) parameter symbol values unit note / test condition number min. typ. max. nominal operating voltage v s 5.5 ? 27 v ? p_5.12.1 pwm frequency of ls f pwm ??25 1) 1) referring to a 47ohm series resistor to charge an external power mos gate khz 2) 2) not subject to production test, specified by design p_5.12.2 table 41 electrical characteristics v s = 5.5 v to 27 v, t j = -40 c to +150 c, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) parameter symbol values unit note / test condition number min. typ. max. overcurrent limitation i lstyp 175 250 325 ma p_5.12.3 on-state resistance 150c r on ??10 ? v s > 5.5 v, i ds =100ma, t j = 150c p_5.12.4 on-state resistance 25c ? 4 ? ? t j = 25c p_5.12.5 leakage current i leakage ??2a0 v < v ls < v s ; t j < 85c p_5.12.6 turn on delay time, slow mode t don-ls ??50s 1) ls_on=1 to 0.9*vs v s =13.5v, r l =270 ? p_5.12.7 turn on delay time, pwm mode t don,f-ls ? ? 0.5 s ls_on=1 to 0.9*vs v s =13.5v, r l =270 ? p_5.12.8 turn on fall time, pwm mode t onf,pwm ?11.25s v ls 0.9*vs to 0.1*vs v s =13.5v, r l =270 ? p_5.12.9 turn on fall time, slow mode t onf,slow ? 100 150 s 1) vls 0.9*vs to 0.1*vs vs=13.5v, rl =270 ? p_5.12.10 turn off delay time, slow mode t doff-ls ??50s 1) ls_on=0 to 0.1*vs v s =13.5v, r l =270 ? p_5.12.11
TLE9833QX electrical characteristics data sheet 90 rev. 1.1, 2012-03-08 turn off delay time, pwm mode t doff,f-ls ? ? 2 s ls_on=0 to 0.1*vs v s =13.5v, r l =270 ? p_5.12.12 turn off rise time, pwm mode t offr,pwm ?11.25s v ls 0.1*vs to 0.9*vs; v s =13.5v, r l =270 ? p_5.12.13 turn off rise time, slow mode t offr,slow ? 100 150 s 1) v ls 0.9*vs to 0.9*vs; v s =13.5v, r l =270 ? p_5.12.14 minimum duty cycle pulse width variation ton min 1.5 2 3.5 s ton(dig) = 2s 2) p_5.12.15 typical (systematic) pulse width increase ls_on to vls d ton typ ? 1.25 ? s ton(dig) = 2s 2) p_5.12.16 zener clamp voltage v az ? 50 ? v values are valid at t j = 25c p_5.12.17 clamping energy (repetitive) e clamp ??2mj 2) 1.000.000 cycles p_5.12.18 clamping energy e clamp ??14mj 2) t start = 25c p_5.12.19 clamping energy (single), hot e clamp ??7mj 2) 10 cycles, t start = 85c p_5.12.20 1) static on mode (no pwm) 2) not subject to production test, specified by design table 41 electrical characteristics (cont?d) v s = 5.5 v to 27 v, t j = -40 c to +150 c, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) parameter symbol values unit note / test condition number min. typ. max.
data sheet 91 rev. 1.1, 2012-03-08 TLE9833QX package outlines 6 package outlines figure 33 package outline vqfn-48-29 notes 1. you can find all of our packages, sorts of packing an d others in our infineon internet page ?products?: http://www.infineon.com/products . 2. dimensions in mm. 0.9 max. seating plane index marking 0.4 x 45 (0.65) index marking 13 12 24 25 48 1 (5.2) 37 36 7 0. 0.03 1 a 6.8 6.8 0.1 48x 0.08 (0.2) 0.05 max. 1) vertical burr 0.03 max. all sides c 7 0.1 b 11 x 0.5 = 5.5 0.5 0.5 11 x 0.5 = 5.5 0.5 0.07 0.15 0.05 (6) (6) (5.2) 0.23 (0.35) m 0.05 0.10 0.05 48x 0.1 a b c pg-vqfn-48-29, -31-po v01 +0.03 1)
TLE9833QX revision history data sheet 92 rev. 1.1, 2012-03-08 7 revision history revision date changes 1.1 2012-03-08 editorial changes 1.1 2012-03-08 added full package name (vqfn-48-29) 1.1 2012-03-08 table 4 : vdd1v5p: power mode configurations: added comment: "power down supply" 1.1 2012-03-08 table 5 : description of pmu submodules: pmu-cycmu description added and pmu-cmu changed from ?cyclic? to ?clock? management 1.1 2012-03-08 table 30 : changed value max. from parameter ?common input voltage in differential mode? from v dd to v ddp 1.1 2012-03-08 table 23 : changed value min. from parameter ?input voltage (amplitude) on xtal1? from 0.3xv ddi to 0.3xv ddp 1.1 2012-03-08 table 41 : for ?turn on..., turn off...? parame ters changed test condition from r l =1k ? to r l =270 ? 1.1 2012-03-08 table 14 : - removed ?max? from the symbol suffixes - corrected symbol of parameter ?input voltage at lin? from v monx to v lin 1.1 2012-03-08 table 41 : parameter ?overcurrent limitation?: - renamed parameter from ?typical on-state current? to ?overcurrent limitation?. - added min. (175ma) and max (325ma) values - removed parameter ?overcurrent threshold accuracy?. this information is added in the ?note/test? condition of the parameter ?overcurrent limitation? 1.1 2012-03-08 table 19 : - renamed parameter ?output current? to ?specified output current? - renamed parameter ?output capacitance ? to ?required output capacitance? 1.1 2012-03-08 table 20 : - renamed parameter ?output current? to ?specified output current? - renamed parameter ?output capacitance ? to ?required output capacitance? - parameter ?dynamic line regulation?: correct typo in ?note/test condition? from v ddc to v ddp - parameter ?output voltage including line regulation @ stop mode?: value max. changed from 1.01 to 1.15 1.1 2012-03-08 figure 31 : application diagram updated 1.1 2012-03-08 figure 29 : module block diagram updated (replaced 500ma by 250ma) 1.1 2012-03-08 table 27 : changed ?maximum output current? to ?nominal output current? in third row 1.1 2012-03-08 table 14 : added ?output voltage vddp? for t < 100ms, in stop mode only 1.1 2012-03-08 chapter 4.1 : added disclaimer note 1.1 2012-03-08 table 11 : changed value c vddext of blocking capacitor at vddext pin to100nf (from 10nf) 1.1 2012-03-08 table 11 and table 12 : changed headline from ?external component requirements? to ?external component recommendation?
data sheet 93 rev. 1.1, 2012-03-08 TLE9833QX revision history trademarks of infineon technologies ag aurix?, c166?, canpak?, ci pos?, cipurse?, econopac k?, coolmos?, coolset?, corecontrol?, crossave?, dave?, easypim?, econobridge?, econ odual?, econopim?, eicedriver?, eupec?, fcos?, hitfet?, hybridpack?, i2rf?, isoface?, isopack?, mipaq?, modstack?, my-d?, novalithic?, optimos?, or iga?, primarion?, prim epack?, primestack?, pro-sil?, profet?, rasic?, reversave?, satric?, sieget?, sindrion?, sipmos?, smartlewis?, solid flash?, tempfe t?, thinq!?, trench stop?, tricore?. other trademarks advance design system? (ads) of agilent te chnologies, amba?, arm?, multi-ice?, keil?, primecell?, realview?, thumb?, vision? of arm limited, uk. autosar? is licensed by autosar development partnership. bluetooth? of bluetooth sig inc. cat-iq? of dect forum. colossus?, firstgps? of trimble navigation ltd. emv? of emvc o, llc (visa holdings in c.). epcos? of epcos ag. flexgo? of microsoft corp oration. flexray? is licensed by fl exray consortium. hyperterminal? of hilgraeve incorporated. iec? of commission electrotec hnique internationale. ir da? of infrared data association corporation. iso? of international organization for standardization. matlab? of mathworks, inc. maxim? of maxim integrated products, inc. microtec?, nucleus? of mentor graphics corporation. mifare? of nx p. mipi? of mipi alliance, inc. mips? of mips technologies, inc., usa. murata? of murata manufacturing co., microwave offi ce? (mwo) of applied wave research inc., omnivision? of omnivision technologies, inc. openwa ve? openwave systems inc. red hat? red hat, inc. rfmd? rf micro devices, inc. sirius? of sirius sate llite radio inc. solaris? of sun microsystems, inc. spansion? of spansion llc ltd. symbian? of symb ian software limited. taiyo yuden? of taiyo yuden co. teaklite? of ceva, inc. t ektronix? of tektroni x inc. toko? of toko kabushiki kaisha ta. unix? of x/open company limited. verilog?, palladium? of cadence design systems, inc. vlynq? of texas instruments inco rporated. vxworks?, wind river? of wind river systems, inc. zetex? of diodes zetex limited. last trademarks update 2011-02-24 1.1 2012-03-08 table 14 : - renamed parameter ?output voltage vddp? to ?voltage vddp? (2x) - renamed parameter ?output vo ltage vddc? to ?voltage vddc? 1.1 2012-03-08 table 28 : added value lin input capacity c lin_in revision date changes
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